2751 0.0

LVDS/TTL PHY & Controller INNOSILICON™ LVDS/TTL IP implements the LVDS TIA/EIA protocol, providing a low-voltage, high-speed point-to-point signal interface. It supports either...

2752 5.0556

A TSMC 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options A key attribute of the Certus 28nm IO library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operatio...

2753 5.0556

1.8V/3.3V Switchable GPIO With 3.3V I2C Open Drain & Analog in TSMC 22nm A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation. The GPIO ce...

2754 1.0

SMIC 55nm sub-LVDS Receiver The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only....

2755 1.0

SMIC 55nm sub-LVDS Receiver The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only....

2756 1.0

ST28nm LVDS Transmitter The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link tra...

2757 5.0556

1.8V/3.3V Switchable GPIO With 5V I2C Open Drain & Analog in TSMC 16nm 16nm & 12nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO, 5V I2C / SMBUS open-drain cell, 5V OTP cell, 1.8V & 3.3V analog cells, an...

2758 200.0

ReRAM NVM in 130nm CMOS, S130 Weebit ReRAM (Resistive Random Access Memory), is an innovative Non-Volatile Memory (NVM) technology that can be easily integrated into any CMOS IC. R...

2759 0.0

LVDS Tx and OpenLDI Tx (Automotive IP) InPsytech Inc., an Automotive interface IP solution provider, introduces its latest Automotive High-Speed Interface IP Series, designed to meet the ri...

2760 10.0

PHYIO for PSRAM memory PHY, 1066Mbps The PHYIOs is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the PSRAM device. The TX is designed to send inf...

2761 0.0

DolphinWare Logic Components Ips Dolphin Technology provides DolphinWare Logic Components IPs, consist of Counters, Registers and MUXs....

2762 5.0

1:2 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

2763 5.0

1:2 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

2764 5.0

1:3 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

2765 5.0

1:3 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

2766 5.0

1:4 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

2767 5.0

1:4 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

2768 5.0

1:6 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

2769 0.0

DolphinWare Verification Ips Dolphin Technology provides DolphinWare Verification IPs (VIPs), consist of AXI4, APB, SD4.0/UHS-II, I2C, I3C, I2S....

2770 5.0

1:3 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

2771 5.0

1:6 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

2772 3.0

Color Camera Sensor Bayer Decoder Today most common single-chip cameras use CMOS sensors with pixels arranged in Bayer color pattern. Bayer filter in front of the sensor embeds color i...

2773 2.0

Floating-point Multiplier High-speed fully pipelined 32-bit floating-point multiplier based on the IEEE 754 standard. Results have a latency of only 4 clock cycles. Ideal for ...

2774 2.0

Floating-point Adder High-speed fully pipelined 32-bit floating-point adder/subtracter based on the IEEE 754 standard. Results have a latency of 5 clock cycles. Ideal f...

2775 2.0

Floating-point Divider High-speed fully pipelined 32-bit floating-point divider based on the IEEE 754 standard. Features a generic latency from 2 to 49 clock cycles. Ideal ...

2776 2.0

Floating-point Square-root High-speed fully pipelined 32-bit floating-point square-root function based on the IEEE 754 standard. Features a generic latency from 2 to 24 clock cy...

2777 2.0

Floating-point to Fixed-point Converter Converts 32-bit floating-point numbers to fixed-point representation. The fixed-point output has a configurable word and fraction width. Floating-poin...

2778 2.0

Cosine Function Function y = cos(x) calculates the cosine of an angle in radians. It has a high-speed, fully pipelined architecture and uses a polynomial with dynamic...

2779 0.0

Floating point adder Floating point adder...

2780 1.0

Sine Function Function y = sin(x) calculates the sine of an angle in radians. It has a high-speed, fully pipelined architecture and uses a polynomial with dynamic c...

2781 2.0

Pipelined Multiplier Function y = a * b is a high-speed multiplier with configurable width and depth. Inputs and outputs may be specified as either signed or unsigned val...

2782 2.0

Pipelined Divider Function y = a / b is a very high-speed divider with configurable dividend and divisor width. Inputs and outputs may be specified as either signed or...

2783 2.0

Pipelined Square Root Function y = √x is a fully scalable square-root function with configurable data width. Inputs and outputs are unsigned integers. An n-bit input valu...

2784 2.0

4-Quadrant Arctan Function Function φ = atan2(y,x) calculates the 4-quadrant inverse tangent in the range -Pi to Pi. Functionally equivalent to the atan2 function in 'C' an...

2785 1.0

SinCos Function Function calculates the Sine and Cosine of input x in radians. Inputs are 18-bit signed values in the range -Pi to Pi. Output values are 17-bit sign...

2786 2.0

Arctan Function Function y = atan(x) calculates the inverse tangent of a fraction. It has a high-speed, fully pipelined architecture and uses a polynomial with dynam...

2787 0.0

Floating point multiplier Floating point multiplier...

2788 0.0

Floating point MAC Floating point MAC...

2789 4.0556

5V ESD Clamp in GlobalFoundries 180nm LPe 5V, ESD clamp in GlobalFoundries 180nm that can be used for either signal protection or 1.8V Power supplies. The clamp is a compact single cell, 44um ...

2790 0.0

GPIO IP GPIO provides general purpose input output interface with AXI, AHB, Avalon and APB, compatible with standard protocol of GPIO specifications. Through ...

2791 4.0556

A radiation-hardened GlobalFoundries 12nm LP/LP+ 0.8V SLVS Transceiver This SLVS I/O Library delivers a robust, high-performance solution for high-speed differential signaling in GlobalFoundries 12nm process technology. D...

2792 0.0

DolphinWare Arithmetic Components Ips Dolphin Technology provides DolphinWare Arithmetic Components IPs, consist of Math Operators and Converters....

2793 0.0

DolphinWare Control Logic Ips Dolphin Technology provides DolphinWare Control Logic IPs, consist of Arbiter and FIFO....

2794 0.0

DolphinWare Data Integrity Ips Dolphin Technology provides DolphinWare Data Integrity IPs, consist of Encoders, Decoders and Error Correction....

2795 10.0

Library of mathematical and floating point (FP) components Optimized for efficient hardware implementation, the Synopsys Foundation Cores include a library of mathematical and floating point (FP) components th...

2796 0.0

Asynchronous FIFO with flags and depth counter ...

2797 0.0

IEEE 754 Floating Point Coprocessor The A2F3 is a fully synthesizable module implemented in Verilog RTL. It is a co-processor unit providing floating-point computation compliant with th...

2798 0.0

Half Precision IEEE-754R complete FPU for graphics processing This block may be used to convert and existing single register stage into a stallable pipeline stage. It can also be used with synchronous RAM blocks...

2799 0.0

Queue Structure The A2Q implements hardware queues for use as FIFOs and LIFOs for inter-process communications, especially in real-time applications. They can be us...

2800 0.0

Register, Configuration and Control Bus A2R provides an interconnection mechanism between control registers in an ASIC design and any number of control devices; CPUs, debug ports etc.. The b...