1001 0.0

APB peripheral implementing the functionality of the ETSI TS 102613 V7.9.0 (2011-03) MAC Layer The eSi-SWP MAC is an APB peripheral and implements the functionality of the ETSI TS 102 613 V7.9.0 (2011-03) MAC Layer....

1002 0.118

APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP Synchronous serial port interface controller with APB interface....

1003 0.118

Direct memory access controller with AHB interface Direct memory access controller with AHB interface....

1004 0.118

APB Fundamental Peripheral IP, I2C controller, Soft IP I2C bus interface controller with APB interface....

1005 0.118

USB 1.1 Device Controller IP, Soft IP USB 1.1 device controller with AHB interface....

1006 0.118

USB 2.0 Device Controller IP, Device controller, Soft IP USB 2.0 device controller....

1007 0.118

USB 1.1.OTG PHY IP, OTG, UMC 0.18um G2 process USB 1.1 On-The-Go transceiver (ECN spec), UMC 0.18um GII Logic process....

1008 0.118

AHB system Peripheral IP, IDE Host controller, Soft IP IDE host controller with AHB interface....

1009 0.118

APB Fundamental Peripheral IP, IO controller, Soft IP General purpose input/output controller with APB interface....

1010 45.0

MIPI D-PHY Universal IP - 4.5Gbps/lane, MIPI D-PHY v2.5 Compliant in TSMC 22ULP The MXL-D-PHY-UNIV-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for...

1011 0.118

APB Fundamental Peripheral IP, Keyboard/Mouse controller, Configurable keypad matrix from 4x4 to 8x16, Soft IP Keyboard/Mouse controller with APB interface....

1012 0.118

AHB system Peripheral IP, SDRAM controller, Soft IP Synchronous DRAM controller with AHB interface....

1013 0.118

AHB system Peripheral IP, SRAM controller, Soft IP Static memory controller with AHB interface....

1014 0.118

SATA II PHY IP, Support SATA Gen1 1.5Gb/s and SATA Gen2 3.0Gb/s, UMC 0.18um Logic process Single channel serial ATA PHY layer compliant with SATA spec. of 3.0Gbps....

1015 0.118

SATA II PHY IP, Gen-2, UMC 0.13um HS/FSG process Serial ATA (SATA) physical layer that provides a complete range of host and device functions, UMC 0.13um HS/FSG Logic process....

1016 0.118

USB 1.1 PHY IP, UMC 0.13um HS/FSG process USB 1.1 PHY, UMC 0.13um HS/FSG Logic process....

1017 0.118

USB 1.1.OTG PHY IP, OTG, UMC 0.13um SP/FSG process USB 1.1 On-The-Go transceiver, UMC 0.13um SP/FSG Logic process....

1018 0.118

USB 2.0 OTG PHY IP, UMC 0.13um HS/FSG process USB 2.0 On-The-Go PHY, UMC 0.13um HS/FSG Logic process....

1019 0.118

USB 1.1 PHY IP, UMC 0.15um SP process USB 1.1 PHY, UMC 0.15um SP Logic process....

1020 0.118

USB 1.1.OTG PHY IP, OTG, UMC 0.15um SP process USB 1.1 On-The-Go transceiver, UMC 0.15um SP Logic process....

1021 0.0

MIPI D-PHY Universal IP in TSMC 65GP The MXL-D-PHY-UNIV-T-65GP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for ...

1022 0.118

SATA II PHY IP, Gen-2, 1 - port, UMC 0.18um G2 process 1.5G/3.0Gbps 1 port Serial ATA PHY and ESATA, UMC 0.18um GII Logic process....

1023 0.118

USB 1.1.OTG PHY IP, OTG, UMC 0.25um Logic process USB 1.1 On-The-Go transceiver (ECN spec), UMC 0.25um Logic process....

1024 0.118

AHB system Peripheral IP, AHB Arbiter, Soft IP The IP is AHB Controller composed of ar-Biter, dECOder and Mux....

1025 0.118

AHB system Peripheral IP, AHB - to - APB Bridge, Soft IP The IP is APB Bridge between AHB bus and APB bus....

1026 0.118

SATA Controller IP, SATA Gen-3 Host, Soft IP SATA AHCI host controller with PVCI/AHB/AXI interface....

1027 0.118

PCI-X Controller IP, PCIX 1.0b, Soft IP PCI-X 1.0b device/host bridge controller....

1028 0.118

USB 2.0 OTG PHY IP, UMC 0.13um LL/FSG process USB 2.0 On-The-Go PHY, UMC 0.13um LL process....

1029 0.118

USB 2.0 OTG Controller IP, Support On-The-Go (Level 3), Soft IP high speed/full speed/low speed USB On-The-Go (level 3) controller with full host function....

1030 0.118

USB 1.1.OTG PHY IP, OTG, UMC 65nm SP process USB 1.1 On-The-Go PHY, UMC 65nm SP/HVT Logic Low-K process....

1031 0.118

USB 1.1.OTG PHY IP, OTG, UMC 90nm SP process USB 1.1 OTG PHY, UMC 90nm SP/RVT Low-K Logic process....

1032 5.0

MIPI D-PHY Universal IP in Samsung 28FDSOI The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY can be configured as a MIPI Master or MIPI Slav...

1033 0.118

AHB system Peripheral IP, External Bus controller, Soft IP External Bus Interface Controller....

1034 0.118

AHB system Peripheral IP, SRAM/ROM Controller, Soft IP Embedded synchronous Single Port SRAM/ROM memory controller with up to two AHB slave ports....

1035 0.118

PCIe Controller IP, PCIe Gen-2 with the AHB interface, x1 Lanes, Soft IP PCI Express Gen 2 Endpoint Controller. Support single-function, virtual channel and single lane....

1036 0.118

AXI Bus Controller IP, Bus Controller, Soft IP Register Slice Controller with AXI bus interface....

1037 0.118

SATA Controller IP, SATA Gen-3, Soft IP SATA Device Controller....

1038 0.118

AXI system Peripheral IP, AXI/APB host bridge, Soft IP AXI/APB host bridge controller....

1039 0.118

PCIe Controller IP, PCIe Gen-2 with the AXI interface, x4 Lanes, Soft IP PCIe Gen2 x4 Lane Endpoint Controller....

1040 0.118

PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY, UMC 0.18um GII Logic (RVT) process....

1041 0.118

PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY, UMC 0.18um GII Logic (RVT) process....

1042 0.118

PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 55nm SP process PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process....

1043 10.0

USB 3.0 femtoPHY in TSMC (28nm, 22nm, 16nm, 12nm) The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer a...

1044 1.0

MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 40ULP The MXL-DPHY-CSI-2-TX+-T-40ULP is a high-frequency, low-power, low-cost, source synchronous physical Layer supporting the MIPI Alliance Specification ...

1045 0.118

PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 90nm SP process PCI-Express II PHY, UMC 90nm SP/RVT Low-K process....

1046 0.118

PCI Express Gen2 PHY IP, PCIe Gen-2, 4 Lanes, UMC 90nm SP process 4x lane PCI Express Gen II PHY, UMC 90nm SP/RVT Low-K Logic process....

1047 0.118

AHB system Peripheral IP, AHB - to - AHB Bridge, Soft IP AHB to AHB bridge....

1048 0.118

AXI system Peripheral IP, DMA controller for AXI master port and slave port (32 - bit, 64 - bit and 128 - bit), 8 channels DMA, Soft IP DMA controller with AXI interface....

1049 0.118

AHB system Peripheral IP, AHB - to - AXI Bridge, Soft IP AHB to AXI bridge....

1050 0.118

AHB system Peripheral IP, Interrupt controller, Soft IP Interrupt controller with AHB interface....