151 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

152 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in GF 28SLP process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol a...

153 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 55LP process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

154 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 65GP process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

155 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

156 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in GF 28SLP process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

157 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 55LP process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

158 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 65GP process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

159 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

160 2.5

Virtex 7 GTX SATA 3 Host Controller The LDS SATA 3 HOST XV7X IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 7 GTX speed grade 2 FPGA. The LDS SA...

161 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in GF 28SLP process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

162 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 55LP process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

163 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 65GP process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

164 3.0

Multi-Link Multi-Protocol SerDes 10Gbps in GF 28SLP Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...

165 3.0

Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 55LP Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...

166 3.0

Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 65GP Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...

167 3.0

MIPI 4.1 M-PHY HS Gear 4 MIPI M-PHY HS Gear 4 IP is compliant with the MIPI serial communication protocol for use in mobile systems where performance, power, and efficiency ar...

168 3.0

High Performance, Low Latency PCIe Gen5 PHY Terminus Circuits offers best-in-class PHY IP for PCI Express Gen 5/4/3/2/1. The PHY is designed for low latency, low power, small form factor, high i...

169 0.0

HDMI ver1.3 Receiver IP HDMI Receiver Link IP Core supporting the standard of HDMI 1.3a, which will be quickly implemented into SoC of consumers; product (HD-TV, AV receiver....

170 0.0

HDMI ver1.3 Transmitter IP HDMI Transmitter Link IP Core supporting the standard of HDMI 1.3a which will be quickly implemented into SoC of consumers' product (HD-TV, AV receive...

171 2.5

SATA HOST 3 ON VIRTEX 7 GTH ...

172 0.0

HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 65/55LP HDMI receiver PHY (Physical layer) is a single-port IP core which is fully compliant with HDMI 1.4 specification. This HDMI RX PHY supports from 25MHz...

173 0.0

HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 65/55GP Physical layer IP core for HDMI transmitters that complies exactly with HDMI 1.4 specifications The HDMI transmitter PHY provides a straight forward i...

174 0.0

HDMI 1.3 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP HDMI receiver PHY (Physical layer) IP is single-port core which is fully compliant with HDMI 1.3a specification. This HDMI Rx PHY supports from 25MHz ...

175 0.0

HDMI 1.3 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP HDMI transmitter PHY (Physical layer) IP core which is fully compliant with HDMI 1.3 specification. The HDMI TX PHY supports from 25MHz to 250MHz pixe...

176 0.0

HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 65/55GP A single-port IP core called the HDMI receiver PHY (Physical layer) is completely compliant with HDMI 1.4's specifications. This HDMI RX PHY provides ...

177 0.0

HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 65/55LP HDMI transmitter PHY (Physical layer) IP core which is fully compliant with HDMI 1.4 specification. HDMI transmitter PHY supports from 25MHz to 250MHz...

178 10.0

MIPI DSI-2 Transmitter v1.1 Controller IP, Compatible with MIPI D-PHY & C-PHY MIPI is the Mobile Industry Processor Interface that provides specification for software and hardware interfaces in mobile terminals and thereby encou...

179 0.0

MIPI UFS v3.1 Device Controller IP, Compatible with M-PHY and Unipro UFS is a high performance, serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash and ...

180 0.0

MIPI UFS v2.1 Host Controller IP, Compatible with M-PHY and Unipro UFS is a high performance, serial interface used in mobile systems to help communicate between host processor and mass storage devices like flash and ...

181 0.0

MIPI Unipro v1.8 Controller IP, Compatible with M-PHY and UFS This MIPI UniPro Controller IP is compliant with the latest MIPI UniPro v1.8 specification, provides the capability to control the UniPro link over a ...

182 2.5

LDS SATA RECORDER ON KINTEX 7 ...

183 0.0

USB 3.0 High/Full/Low-Speed Host + Device Controller IP USB 3.0 Dual Mode Controller IP Core uses a high performance DMA engine based on the xHCI specification and presenting either an AHB or AXI interface,...

184 0.0

PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP This Peripheral Component Interconnect Express Gen3 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 interface spec. Low pow...

185 0.0

USB 3.0 Gen1 / Gen2 Device Controller IP We provide highly configurable and scalable USB 3.0 host/device/dual mode controller IP Core for a wide range of applications. The USB 3.0 controller ...

186 0.0

USB 3.1 Gen1 / Gen2 Device Controller IP USB 3.1 Device controller is a highly configurable core and implements the USB 3.1 Device functionality that can be interfaced with third party USB 3....

187 0.0

Display Port 1.2 Tx PHY & Controller IP (Silicon Proven in STMicro 28FDSOI) Our Display Port is VESA DP1.1a, DP1.2 and eDP compliant with four main lanes and an auxiliary channel The DP transmitter acceptsDP1.1a HBR (2.7Gbps) ...

188 0.0

MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP Version 1.2 of the D-PHY specification is completely complied with by the MIPI D-PHY Analog TX IP Core. It is compatible with the Display Serial Inter...

189 0.0

USB 3.0 OTG High / Full / Low- Speed Dual Role IP Core USB 3.0 OTG Controller IP is based on the latest USB 3.0 specification from USB Implementer Forum (USB?IF) and is compatible with the latest xHCI 1.1 ...

190 0.0

MIPI M-PHY v3.1 IP, Silicon Proven in TSMC 28HPC+ The MIPI M-PHY Gear 3 IP is compliant with the latest MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v3.0 Specification, Uni...

191 0.0

HDMI - Display Port Combo PHY IP, Silicon Proven in TSMC 28HPC+ The DisPlay Port/HDMI/DVI Receiver is a high performance combo PHY with Display Port Receiver and HDMI Receiver. In DisPlay Port mode, the receiver is...

192 0.0

ISO 7816 based Smart Card Reader IP The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications. It provides a communication interface with a sm...

193 2.5

SATA 3 Host Controller on Xilinx Artix 7 The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS_SATA3_HO...

194 0.0

USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+ The combination PHY comprises of a Serial ATA (SATA) compliant with the SATA 3.0 Specification, a Peripheral Component Interconnect Express (PCIe) com...

195 0.0

Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+ Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR Bandwidth, Equalizer s...

196 55.0

USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core Our company offers a highly configurable and adaptable USB 2.0 OTG controller IP core, suitable for a wide range of applications. This controller adhe...

197 0.0

USB 1.1 Device Controller IP USB 1.1 Device Controller IP is based on the latest USB 1.1 specification from USB Implementer Forum (USB-IF) and is compatible with the latest xHCI 1...

198 0.0

USB 2.0 PHY IP, Silicon Proven in TSMC 28HPC+ The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption. For usage with either hosts, dev...

199 0.0

USB 2.0 Host (xHCI) Controller IP We provide highly configurable and scalable USB 2.0 host/ device/dual-mode controller IP Cores for a wide range of applications. The USB 2.0 controlle...

200 0.0

USB 3.0 Gen1 / Gen2 Host Controller IP We provide highly configurable and scalable USB 3.1 host/device/dualmode controller IP Cores for a wide range of applications. The USB3.0 host control...