1601 0.0

AHB to AXI Bridge IP SmartDV’s AHB to AXI Bridge IP Core provides a seamless interface between AMBA AHB and AXI protocols, enabling smooth integration of legacy AHB-based ...

1602 0.0

APB Multilayer Interconnect IP SmartDV’s APB (Advanced Peripheral Bus) Multilayer Interconnect IP enables efficient communication between multiple APB masters and slaves, streamlini...

1603 0.0

APB to AHB Bridge IP SmartDV’s APB to AHB Bridge IP enables seamless communication between low-bandwidth peripheral devices on the APB (Advanced Peripheral Bus) and high-p...

1604 0.0

APB to AXI Bridge IP SmartDV’s APB to AXI Bridge IP enables seamless protocol conversion between the low-bandwidth APB (Advanced Peripheral Bus) and the high-performance A...

1605 0.0

DMA AXI4-Stream Interface to AXI Memory Map Address Space Digital Blocks DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog RTL IP Core accepts AXI4-Stream data and control input, converts the control TID to a AXI4 Mem...

1606 0.0

AXI Multilayer Interconnect IP SmartDV’s AXI Multilayer Interconnect IP is a high-throughput, silicon-proven solution designed to manage complex on-chip communication between multip...

1607 0.0

AXI to AHB Bridge IP SmartDV’s AXI to AHB Bridge IP enables seamless interoperability between AMBA AXI and AMBA AHB protocols, allowing efficient data transfer across syst...

1608 0.0

AXI to APB Bridge IP SmartDV’s AXI to APB Bridge IP enables seamless communication between high-performance AXI-based systems and simpler, lower-power APB peripherals. It ...

1609 0.0

AXI to UCIe Bridge IP SmartDV’s AXI to UCIe Bridge IP enables seamless integration between standard AMBA AXI-based SoC architectures and the emerging UCIe (Universal Chiple...

1610 0.0

CHI to UCIe Bridge IP SmartDV’s CHI to UCIe Bridge IP enables seamless protocol translation between Arm’s Coherent Hub Interface (CHI) and the Universal Chiplet Interconnec...

1611 0.0

CXL 2.x Controller IP SmartDV’s CXL (Compute Express Link) 2.0 Controller IP extends support for advanced memory pooling, switching, and persistent memory, enhancing scalab...

1612 0.0

CXL 3.x Controller IP SmartDV’s CXL (Compute Express Link) 3.x Controller IP brings high-speed, coherent connectivity with enhanced fabric capabilities—supporting memory-ce...

1613 0.0

CXL to UCIe Bridge IP SmartDV’s CXL to UCIe Bridge IP enables seamless interoperability between Compute Express Link (CXL) and Universal Chiplet Interconnect Express (UCIe)...

1614 0.0

CXS to UCIe Bridge IP SmartDV’s CXS to UCIe Bridge IP enables seamless connectivity between chiplet-based designs and traditional SoC architectures by bridging AMBA CXS int...

1615 0.0

AXI4 Memory Map to AXI4-Stream Bridge Digital Blocks DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog RTL IP Core accepts AXI4 Memory Map address, control, and data input, converts the address to ...

1616 0.0

DisplayPort 2.x Receiver IP SmartDV’s DisplayPort 2.x Receiver IP is a silicon-proven, high-performance solution built to support next-generation display and video applications a...

1617 0.0

DisplayPort 2.x Transmitter IP SmartDV’s DisplayPort 2.x Transmitter IP is a silicon-proven, high-performance solution designed to enable cutting-edge video transmission in consumer...

1618 9.5077

PCIe 5.0 PHY (8nm) The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 5.x specification. This IP offers a cost-effective and low-power so...

1619 9.5077

PCIe 5.0 PHY (5nm) The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 5.x specification. This IP offers a cost-effective and low-power so...

1620 9.5077

PCIe 5.0 PHY (4nm) The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 5.x specification. This IP offers a cost-effective and low-power so...

1621 0.0

eUSB 2.0 PHY in TSMC (N5, N4P, N4C, N3P, N2P) Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...

1622 0.0

MIPI MPHY G6 2TX2RX in Samsung (SF5A, SF2P) The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v4.1 specification, supports multiple gears and a broad range of high...

1623 0.0

USB2 Device Controller The Synopsys USB 2.0 Device Controller enables ASIC/FPGA designers to implement a complete USB 2.0 Device interface. The USB 2.0 Device supports USB H...

1624 0.0

I3C Master Controller w/FIFO (APB Bus) The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...

1625 0.0

HDMI 2.1/DisplayPort eDP 1.4 TX PHY in TSMC (N6C, N4C) The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...

1626 20.0

eUSB2V2.0 IP Arasan Chip Systems, the leading provider of IP for Mobile and Automobile SOC’s, presents its latest eUSB2 V2.0 IP. eUSB2 V2.0 is a new generation spe...

1627 0.0

Synopsys USB-C 3.1/DP TX PHY for TSMC N4P The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...

1628 0.0

Synopsys MIPI C-PHY v1.2 D-PHY v2.1 for TSMC N4P Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

1629 50.0

Ultra-Low Latency 32Gbps SerDes Phy IP in 22 nm As real-time workloads—from high-frequency trading to low-latency AI and edge analytics—push system responsiveness to the limit, every nanosecond coun...

1630 4.5077

MIPI C-PHY 8Gsps / D-PHY 9Gbps TRX Combo PHY (SF2P) The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...

1631 0.0

Synopsys PCIe 7.0 PHY IP for SF4X The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...

1632 0.0

I3C Slave Controller w/FIFO (APB Bus) The Digital Blocks DB-I3C-S-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improve...

1633 6.0

DS22: 32Gbps SerDes PHY in GlobalFoundries 22FDX A 32Gbps (with 16Gbps mode) protocol-agnostic SerDes PHY in GlobalFoundries 22FDX, for advanced mixed-signal and high-speed digital SoCs. Modular arch...

1634 0.0

Synopsys MIPI C-PHY v2.0 D-PHY v2.1 TX for TSMC N6 Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

1635 6.0

AXI2APB Bridge Truechip's AXI2APB IP provides chip designers and architects, an efficient way to connect AXI & APB based IPs with reduced latency, power, and area....

1636 6.0

AHB2APB Bridge IP Truechip's AHB2APB Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency...

1637 0.0

Synopsys eUSB2V2 Device Controller IP Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...

1638 0.0

MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in GlobalFoundries (12nm) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

1639 0.0

PCIe 5.0 PHY in GlobalFoundries (12nm) The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...

1640 0.0

Synopsys Complete UFS 5.0 solution with UniPro 3.0 + M PHY v6.0 enables Gear6B 46.7 Gb/s, reduced power, and high bandwidth scalability The Synopsys Universal Flash Storage (UFS) Host Controller IP is a standardbased serial interface engine for implementing the JEDEC UFS interface in c...

1641 0.0

Synopsys High speed M PHY v6.0 delivers 46.7 Gb/s Gear6B, enhanced channel robustness, low power modes, and integration with UniPro/UFS The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v6.0 specification, supports speeds up to 46.7 Gbps per lane. The IP ...

1642 20.0

Network on Chip (NoC) A Network-on-Chip (NoC) is a scalable on-chip communication fabric that connects multiple initiators and targets using packet-based routing. Unlike a ...

1643 0.0

AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA The Digital Blocks DB-SPI-FLASH-CTRL is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad SPI Flash...

1644 30.0

Gen6-AglxTM Mobiveil’s Gen6-Aglx Accelerator platform is a PCIe® Gen6 add-in card with latest Intel’s Agilex I series FPGA. It supports High-Performance Applicat...

1645 0.0

Synopsys MIPI UniPro v3.0 Controller IP Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...

1646 0.0

112G Multi-Rate SerDes Empowering customers to thrive in the AI era, INNOSILICON™ introduces its most advanced 112G SerDes (Serializer/Deserializer) and Controller IP, purpo...

1647 1.0

UFS 5.0 Host Controller compatible with M-PHY 6.0 and UniPro 3.0 Universal Flash Storage (UFS) is a JEDEC standard for high performance mobile storage devices suitable for next generation data storage. UFS is also a...

1648 6.5077

MIPI CSI-2 TX Controller The Cameta Serial Interface 2 (CSI-2) Transmitter (TX) Controller is a digital core that implements all protocol functions defined in the MIPI Allianc...

1649 0.0

AHB to Parallel Bridge for Audio CODEC dos_AHB_parallel_bridge is a Parallel interface for Codec connection. Support for multiple channels. Each channel includes a FIFO accessible from para...

1650 0.0

HDMI 2.1 Rx PHY in TSMC (N6C) The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide th...