Atria Logic, Inc. IP Cores

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501

0.118

UMC 55nm eFlash/LVT Logic Process 7-track Genernic Core cell library

UMC 55nm eFlash/LVT Logic Process 7-track Genernic Core cell library...

502

0.118

UMC 55nm eFlash/LVT Logic Process 7-track PowerSlash Kit cell library

UMC 55nm eFlash/LVT Logic Process 7-track PowerSlash Kit cell library...

503

0.118

UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library

UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library...

504

0.118

UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library

UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library...

505

0.118

UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library

UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library...

506

0.118

UMC 55nm eFlash/RVT Logic Process 7-track ECO_M1 cell library

UMC 55nm eFlash/RVT Logic Process 7-track ECO_M1 cell library...

507

0.118

UMC 55nm eFlash/RVT Logic Process 7-track Genernic Core cell library

UMC 55nm eFlash/RVT Logic Process 7-track Genernic Core cell library...

508

0.118

UMC 55nm eFlash/RVT Logic Process 7-track PowerSlash Kit cell library

UMC 55nm eFlash/RVT Logic Process 7-track PowerSlash Kit cell library...

509

0.118

UMC 55nm eFlash/RVT Logic Process High Speed 12-track ECO_M1 cell library

UMC 55nm eFlash/RVT Logic Process High Speed 12-track ECO_M1 cell library...

510

0.118

UMC 55nm eFlash/RVT Logic Process High Speed 12-track Genernic Core cell library

UMC 55nm eFlash/RVT Logic Process High Speed 12-track Genernic Core cell library...

511

0.118

UMC 55nm eFlash/RVT Logic Process High Speed 12-track PowerSlash Kit cell library

UMC 55nm eFlash/RVT Logic Process High Speed 12-track PowerSlash Kit cell library...

512

0.118

UMC 55nm eFlash/RVT LowK Logic Process 8-track ECO_M1 cell Library

UMC 55nm eFlash/RVT LowK Logic Process 8-track ECO_M1 cell Library...

513

0.118

UMC 55nm eFlash/RVT LowK Logic Process 8-track Genernic Core cell Library

UMC 55nm eFlash/RVT LowK Logic Process 8-track Genernic Core cell Library...

514

0.118

UMC 55nm eFlash/RVT LowK Logic Process 8-track PowerSlash Kit cell Library

UMC 55nm eFlash/RVT LowK Logic Process 8-track PowerSlash Kit cell Library...

515

0.118

UMC 55nm Logic and Mixed-Mode Ultra Low Power / HVT Low-K Process 5V Tolerant BOAC I/O cell library

UMC 55nm Logic and Mixed-Mode Ultra Low Power / HVT Low-K Process 5V Tolerant BOAC I/O cell library...

516

0.118

UMC 55nm Logic and Mixed-Mode Ultra Low Power Low-K Process 1.8V/2.5V/3.3V multi-voltage BOAC I/O cell library

UMC 55nm Logic and Mixed-Mode Ultra Low Power Low-K Process 1.8V/2.5V/3.3V multi-voltage BOAC I/O cell library...

517

0.118

UMC 55nm Logic process standard synchronous Contact ROM memory compiler.

UMC 55nm Logic process standard synchronous Contact ROM memory compiler....

518

0.118

UMC 55nm Logic process standard synchronous Contact ROM memory compiler.

UMC 55nm Logic process standard synchronous Contact ROM memory compiler....

519

0.118

UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler.

UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler....

520

0.118

UMC 55nm LP/LVT Logic Process MPCA cell library_x005F_x005F_x005F_x005F_x005F_x000D_ _x005F_x005F_x005F_x005F_x005F_x000D_

UMC 55nm LP/LVT Logic Process MPCA cell library...

521

0.118

UMC 55nm LP/RVT Logic Process MPCA cell library_x005F_x005F_x005F_x005F_x005F_x000D_

UMC 55nm LP/RVT Logic Process MPCA cell library...

522

0.118

UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%.

UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%....

523

0.118

UMC 55nm LP/RVT LowK Logic Process 2.5VOD3.3V device RTC Core Library

UMC 55nm LP/RVT LowK Logic Process 2.5VOD3.3V device RTC Core Library...

524

0.118

UMC 55nm SP-RVT 1P10M Logic Process 1.8V/3.3V multi-voltage BOAC I/O cell library

UMC 55nm SP-RVT 1P10M Logic Process 1.8V/3.3V multi-voltage BOAC I/O cell library...

525

0.118

UMC 55nm SP/RVT LowK Logic Process True 3.3V Generic IO Cell Library

UMC 55nm SP/RVT LowK Logic Process True 3.3V Generic IO Cell Library...

526

0.118

UMC 55nm SP/RVT LowK Logic Process True 3.3V Low Frequency OSC IO Cell Library

UMC 55nm SP/RVT LowK Logic Process True 3.3V Low Frequency OSC IO Cell Library...

527

0.118

UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler.

UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler....

528

0.118

UMC 55nm Standard Performance LowK Logic Process Two-Port Register File

UMC 55nm Standard Performance LowK Logic Process Two-Port Register File...

529

0.118

UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery

UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery...

530

0.118

UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT

UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT...

531

0.118

UMC 55nm uLP LowK Logic Process Ture 3.3V Generic IO Cell Library

UMC 55nm uLP LowK Logic Process Ture 3.3V Generic IO Cell Library...

532

0.118

UMC 55nm ULP LowK Logic Process Ture 3.3V high Frequency OSC IO Cell Library

UMC 55nm ULP LowK Logic Process Ture 3.3V high Frequency OSC IO Cell Library...

533

0.118

UMC 55nm uLP LowK Logic Process Ture 3.3V Low Frequency OSC IO Cell Library

UMC 55nm uLP LowK Logic Process Ture 3.3V Low Frequency OSC IO Cell Library...

534

0.118

UMC 55nm uLP LowK Logic Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library

UMC 55nm uLP LowK Logic Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library...

535

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell...

536

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell...

537

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell...

538

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90). W/O deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90). W/O deep Nwell....

539

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell...

540

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60).W/O deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60).W/O deep Nwell....

541

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90)

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90)...

542

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

543

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell...

544

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell...

545

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90)

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90)...

546

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

547

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...

548

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell...

549

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell...

550

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90). W/O deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90). W/O deep Nwell....

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