Design & Reuse
Catalog of SIP Cores
System on Chip design resources
3747 IP
2251
0.118
UMC 55NM SP-RVT with 2.5V device DDR23 COMBO PHY CMD/ADDR Block for 2 layer PCB board usage
UMC 55NM SP-RVT with 2.5V device DDR23 COMBO PHY CMD/ADDR Block for 2 layer PCB board usage...
2252
0.118
UMC 55NM SP-RVT with 2.5V device process 16BIT DDR23 COMBO DATA PHY for two layer PCB board usage
UMC 55NM SP-RVT with 2.5V device process 16BIT DDR23 COMBO DATA PHY for two layer PCB board usage...
2253
0.118
UMC 55nm SP/RVT LowK Logic Process True 3.3V Generic IO Cell Library
UMC 55nm SP/RVT LowK Logic Process True 3.3V Generic IO Cell Library...
2254
0.118
UMC 55nm SP/RVT LowK Logic Process True 3.3V Low Frequency OSC IO Cell Library
UMC 55nm SP/RVT LowK Logic Process True 3.3V Low Frequency OSC IO Cell Library...
2255
0.118
UMC 55nm SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm SST process standard synchronous high density single port SRAM memory compiler....
2256
0.118
UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler.
UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler....
2257
0.118
UMC 55nm Standard Performance LowK Logic Process Two-Port Register File
UMC 55nm Standard Performance LowK Logic Process Two-Port Register File...
2258
0.118
UMC 55nm ULP Low-K process HVT via1 ROM
UMC 55nm ULP Low-K process HVT via1 ROM...
2259
0.118
UMC 55nm ULP Low-K process One Port Register File for periphery HVT
UMC 55nm ULP Low-K process One Port Register File for periphery HVT...
2260
0.118
UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT
UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT...
2261
0.118
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery...
2262
0.118
UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT
UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT...
2263
0.118
UMC 55nm uLP LowK Logic Process Ture 3.3V Generic IO Cell Library
UMC 55nm uLP LowK Logic Process Ture 3.3V Generic IO Cell Library...
2264
0.118
UMC 55nm ULP LowK Logic Process Ture 3.3V high Frequency OSC IO Cell Library
UMC 55nm ULP LowK Logic Process Ture 3.3V high Frequency OSC IO Cell Library...
2265
0.118
UMC 55nm uLP LowK Logic Process Ture 3.3V Low Frequency OSC IO Cell Library
UMC 55nm uLP LowK Logic Process Ture 3.3V Low Frequency OSC IO Cell Library...
2266
0.118
UMC 55nm uLP LowK Logic Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library
UMC 55nm uLP LowK Logic Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library...
2267
0.118
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT...
2268
0.118
UMC 55nm ULP process PG-One Port Register File for periphery HVT
UMC 55nm ULP process PG-One Port Register File for periphery HVT...
2269
0.118
UMC 55nm ULP process ROM compiler with HVT peripheral
UMC 55nm ULP process ROM compiler with HVT peripheral...
2270
0.118
UMC 55nm ULP-SST process PG One Port Register File for periphery HVT
UMC 55nm ULP-SST process PG One Port Register File for periphery HVT...
2271
0.118
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler....
2272
0.118
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler....
2273
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
2274
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell...
2275
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell...
2276
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90). W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90). W/O deep Nwell....
2277
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
2278
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60).W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60).W/O deep Nwell....
2279
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90)
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90)...
2280
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
2281
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
2282
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell...
2283
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90)
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90)...
2284
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
2285
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...
2286
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell...
2287
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell...
2288
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90). W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90). W/O deep Nwell....
2289
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell....
2290
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60). W/O deep Nwell...
2291
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....
2292
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90). W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90). W/O deep Nwell....
2293
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell....
2294
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell...
2295
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell...
2296
0.118
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell.
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell....
2297
0.118
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM...
2298
0.118
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM...
2299
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler...
2300
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler...