Design & Reuse
4331 IP
1651
0.118
PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 55nm SP process
PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process....
1652
0.118
PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 90nm SP process
PCI-Express II PHY, UMC 90nm SP/RVT Low-K process....
1653
0.118
PCI Express Gen2 PHY IP, PCIe Gen-2, 4 Lanes, UMC 90nm SP process
4x lane PCI Express Gen II PHY, UMC 90nm SP/RVT Low-K Logic process....
1654
0.118
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.13um HS/FSG process
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY with Low Power feature, UMC 0.13um HS/FSG Logic process....
1655
0.118
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY, UMC 0.18um GII Logic (RVT) process....
1656
0.118
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY, UMC 0.18um GII Logic (RVT) process....
1657
0.118
PCI-X Controller IP, PCIX 1.0b, Soft IP
PCI-X 1.0b device/host bridge controller....
1658
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PCIe Controller IP, PCIe Gen-2 with the AHB interface, x1 Lanes, Soft IP
PCI Express Gen 2 Endpoint Controller. Support single-function, virtual channel and single lane....
1659
0.118
PCIe Controller IP, PCIe Gen-2 with the AXI interface, x4 Lanes, Soft IP
PCIe Gen2 x4 Lane Endpoint Controller....
1660
0.118
SD Host Controller IP, SD host spec. v3.0, SDIO spec. v2.0, MMC spec. v4.3, Supports UHS50/UHS104 card, Soft IP
SD host controller wih ahb interface, compliant with the SD Host Controller Standard Specification Version 3.00....
1661
0.118
DDR DLL (All Digital) IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...
1662
0.118
DDR DLL IP, 100MHz - 200MHz, Output: 13.5% - 36.6% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhanceme...
1663
0.118
DDR DLL IP, 100MHz - 400MHz, Output: 25% Delay, UMC 0.13um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.13um HS/FSG process....
1664
0.118
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic ...
1665
0.118
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/RVT Logic process....
1666
0.118
DDR DLL IP, Input: 100MHz - 150MHz, Output: 100MHz - 150MHz, UMC 0.18um G2 process
Input 100M-150MHz, output 100M-150MHz, DDR DLL, UMC 0.18um GII Logic process....
1667
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.13um HS/FSG process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.13um HS/FSG Logic process....
1668
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.15um SP process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.15um SP Logic process....
1669
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.162um LL process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.162um Logic process....
1670
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz -200MHz, UMC 0.18um G2 process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.18um GII Logic process....
1671
0.118
DDR DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 65nm SP process
Input 100-400MHz, output 100-400MHz, DDR2 DLL, UMC 65nm SP/RVT Low-K Logic process....
1672
0.118
DDR DLL IP, Input: 192MHz - 400MHz, Output: 96MHz - 200MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG process DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage....
1673
0.118
DDR DLL IP, Input: 200MHz - 333MHz, Output: 200MHz - 333MHz, UMC 90nm SP process
Input 200-333MHz, output 200-333MHz, DDR2 DLL, UMC 90nm SP/RVT Low-K Logic process....
1674
0.118
DDR DLL IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, UMC 55nm SP process
Input 200-400MHz, output 200-400MHz, DDR2 DLL, UMC 55nm SP Low-K Logic process....
1675
0.118
DDR DLL IP, Input: 333MHz - 667MHz, Output: 333MHz - 667MHz, UMC 90nm SP process
Input 333M-667MHz, output 333M-667MHz, DDR2/3 Multi-phase DLL, UMC 90nm SP/RVT Low-K Logic process....
1676
0.118
DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
It is a UMC 0.13um HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller usage....
1677
0.118
DDR DLL IP, Input: 66MHz - 133MHz, Output: 66MHz - 133MHz, UMC 0.13um HS/FSG process
Input 66M-133MHz, output 66M-133MHz, DDR DLL, UMC 0.13um HS/FSG Logic process....
1678
0.118
DDR DLL IP, Input: 66MHz - 200MHz, Output: 66MHz - 200MHz, UMC 90nm SP process
Input 66M-200MHz, output 66M-200MHz, DDR DLL, UMC 90nm SP/RVT Low-K Logic process....
1679
0.118
DDR DLL IP, Input: 80MHz - 320MHz, Output: 6.25%-50% Delay, UMC 55nm SP process
Input 80-320MHz, output 6.25%~50% delay, 80-320MHz, DDR2 DLL, UMC 55nm SP/RVT Low-K Logic process....
1680
0.118
DDR2/3 Controller IP, DDR2/3 controller with DFI 2.1 interfaces, Support DDR1/DDR2/DDR3 SDRAM, Soft IP
DDR2/3 Combo SDRAM Controller....
1681
0.118
Memory Controller IP, Memory Stick controller, Soft IP
Memory Stick host controller with AHB Bus....
1682
0.118
Memory Controller IP, NAND Flash memory Host controller, Soft IP
NAND flash host controller with AHB interface, it supports SLC and MLC NAND flash....
1683
0.118
General Purpose IO IP, 1.8V BOAC EMMC I/O, Support built-in Pull-Up / Pull-Down , UMC 28nm HLP process
UMC 28nm Logic and Mixed-Mode HLP/RVT process 1.8V BOAC EMMC IO Cell Library (with customized PU/PD function)....
1684
0.118
General Purpose IO IP, 1.8V Operations, UMC 0.18um eHV process
UMC 0.18um Embedded High-Volatge process,1.8V IO Cells....
1685
0.118
General Purpose IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process mini IO (blown up version of 0.18u Mini-IO)....
1686
0.118
General Purpose IO IP, 1.8V/2.5V/3.3V Operations, UMC 90nm SP process
UMC 90nm SP/RVT Low-K process 2.5V over-drive 3.3V GOX52 process IO....
1687
0.118
General Purpose IO IP, 3.3V Operations, 5V input tolerance, UMC 0.18um Mixed-Mode process
UMC 0.18um Mixed-Mode / RFCMOS process 5V tolerance standard IO Cell Library....
1688
0.118
General Purpose IO IP, 3.3V Operations, BOAC (Bonding Over Active Circuit), UMC 0.18um LL process
UMC 0.18um LL Logic process true 3.3V Generic IO cell For BOAC....
1689
0.118
General Purpose IO IP, 3.3V Operations, UMC 0.18um Mixed-Mode process
UMC 0.18um Mixed-Mode / RFCMOS process true 3.3V standard IO Cell Library....
1690
0.118
General Purpose IO IP, 3.3V tolerance, UMC 0.25um Logic process
UMC 0.25um Logic process 3.3V tolerance standard IO Cell Library....
1691
0.118
General Purpose IO IP, 3.3V tolerance, UMC 0.25um Logic process
UMC 0.25um Logic process Generic 3.3V Tolerant IO cells....
1692
0.118
General Purpose IO IP, 3.3V tolerance, UMC 90nm LL process
UMC 90nm LL/RVT process 3.3V tolerant IO Cell Library....
1693
0.118
General Purpose IO IP, 3.3V tolerance, UMC 90nm LL process
UMC 90nm LL/RVT process 3.3V tolerant IO Cell Library....
1694
0.118
General Purpose IO IP, 3.3V tolerance, UMC 90nm SP process
UMC 90nm Low-K SP process 3.3V tolerant IO Cell Library....
1695
0.118
General Purpose IO IP, 3.3V tolerance, UMC 90nm SP process
UMC 90nm SP/RVT process 3.3V tolerant IO Cell Library....
1696
0.118
General Purpose IO IP, 3.3V with 5V tolerance, Power-On Control, BOAC (Bonding Over Active Circuit) support, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 5V Tolerance Generic POC IO with BOAC solution....
1697
0.118
General Purpose IO IP, 5V input tolerance, UMC 0.18um CIS process
UMC 0.18um CMOS Image Sensor process 3.3V with 5V tolerance standard IO Cell Library....
1698
0.118
General Purpose IO IP, 5V input tolerance, UMC 0.18um G2 process
UMC 0.18um GII Logic process 3.3V with 5V tolerance IO Cell Library...
1699
0.118
General Purpose IO IP, 5V input tolerance, UMC 0.18um G2 process
UMC 0.18um GII Logic process 5V tolerance standard IO Cell Library....
1700
0.118
General Purpose IO IP, 5V input tolerance, UMC 0.18um LL process
UMC 0.18um LL Logic process 5V tolerance standard IO Cell Library....