Low Power Futures IP Cores

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UMC 40nm Low Power Process One Port Register File with 213 cell

UMC 40nm Low Power Process One Port Register File with 213 cell...

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UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell

UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell...

253

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UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating

UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating...

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UMC 40nm Low Power Process Single-Port SRAM for dual power rail

UMC 40nm Low Power Process Single-Port SRAM for dual power rail...

255

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UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell

UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell...

256

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UMC 40nm Low Power Process SP-SRAM with 213 bit cell

UMC 40nm Low Power Process SP-SRAM with 213 bit cell...

257

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UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral.

UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral....

258

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UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with LVT peripheral.

UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with LVT peripheral....

259

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UMC 40nm Low Power Process Ultra High Speed One Port Register File memory compiler with dual rail

UMC 40nm Low Power Process Ultra High Speed One Port Register File memory compiler with dual rail...

260

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UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler

UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler...

261

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UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler

UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler...

262

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UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler

UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler...

263

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UMC 40nm ultra low power via1 ROM complier

UMC 40nm ultra low power via1 ROM complier...

264

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UMC 55nm eFlash process process synchronous low power feature RVT peripheral high density single port SRAM compiler.

UMC 55nm eFlash process process synchronous low power feature RVT peripheral high density single port SRAM compiler....

265

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UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy.

UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy....

266

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UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Generic IO Cell Library

UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Generic IO Cell Library...

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UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library

UMC 55nm Embedded Flash and Embedded E2PROM Low Power Low-K Split-Gate Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library...

268

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UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy.

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...

269

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UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler.

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...

270

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UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy.

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...

271

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UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler.

UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...

272

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UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process_x005F_x005F_x005F_x005F_x005F_x000D_

UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process...

273

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UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias

UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias...

274

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UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias

UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias...

275

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UMC 55nm Logic and Mixed-Mode Ultra Low Power / HVT Low-K Process 5V Tolerant BOAC I/O cell library

UMC 55nm Logic and Mixed-Mode Ultra Low Power / HVT Low-K Process 5V Tolerant BOAC I/O cell library...

276

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UMC 55nm Logic and Mixed-Mode Ultra Low Power Low-K Process 1.8V/2.5V/3.3V multi-voltage BOAC I/O cell library

UMC 55nm Logic and Mixed-Mode Ultra Low Power Low-K Process 1.8V/2.5V/3.3V multi-voltage BOAC I/O cell library...

277

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UMC 55nm uLP LowK Logic Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library

UMC 55nm uLP LowK Logic Process Ture 3.3V Low Power Low Frequency OSC IO Cell Library...

278

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Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.

Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process....

279

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Low power 12bit 4Msps SAR ADC with UMC 55nm EFLASH Process

Low power 12bit 4Msps SAR ADC with UMC 55nm EFLASH Process...

280

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Low power LVDS Receiver 800Mbps; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

Low power LVDS Receiver 800Mbps; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...

281

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Low power LVDS Receiver IO 50Mbps; UMC 0.11 um Logic HS/FSG (Cu) Process

Low power LVDS Receiver IO 50Mbps; UMC 0.11 um Logic HS/FSG (Cu) Process...

282

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USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process

USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process...

283

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1 Port High-Current Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option

1 Port Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...

284

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2 Port High-Density Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option

2 Port High-Density Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...

285

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1 Port Multi-Bank Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option

1 Port Multi-Bank Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...

286

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1-56G-PCIe Gen5 ePHY Multi-Protocol SerDes IP - 7nm Low Power and Latency

Ultra-high speed SerDes IP, adopted by global Tier-1 network/storage/5G OEMs and major semiconductor companies. eTopus is the pioneer on PAN4 ADC/DSP...

287

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H.264 hardware encoder for ultra low power IoT application

...

288

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H.264 Low Power & Low Latency Hardware Video Decoder IP Core

The Atria Logic AL-H264D-HW is a hardware-based, low power, low latency, feature-rich, H.264 (AVC) Baseline Profile video decoder IP core, targeted fo...

289

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3.3V - >1.2V/1.1V/0.9V Low Power Cap-less LDO IP Core

A 3.3V - >1.2V/1.1V/0.9V Low Power Cap-less LDO (Low Drop-Out) is a type of voltage regulator designed to provide a stable output voltage of 0.9 volts...

290

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3.3V->1.5V Low Power LDO IP Core

A 3.3V->1.5V Low Power LDO (Low Drop-Out) is a type of voltage regulator designed to provide a stable output voltage of 1.5 volts from a 3.3-volt inpu...

291

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1.8V->0.8V Low Power LDO IP Core

A 1.8V -> 0.8V low power LDO (Low Drop-Out) is a type of voltage regulator designed to provide a stable output voltage of 0.8 volts from a 1.8-volt in...

292

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10 bit 3Msps Ultra low power SAR ADC IP core

High performance, 10-bit resolution, 3-Msps sample rate Ultra Low Power Mixed-signal SAR ADC IP Core. Leading edge systems on chip (SoCs) for microcon...

293

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400MHz Integer-N Low power PLL

This is an analog Integer-N PLL frequency synthesizer, which can generate independent clock with frequency range from 6.25MHz to 800MHz.It supports 4M...

294

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802.11 BGN Low Power WIFI RF SoC

The Silicon chip supports 802.11bgn, 20Mhz/40Mhz standard.It supports PWM up to 6 channel, Co-existance interface to BLE / Zigbee chip. The chip in...

295

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10bit 100Ksps low power SAR ADC IP core

High performance, 10-bit resolution, 100 Ksps sample rate Ultra Low Power Mixed-signal SAR ADC IP Core. Leading edge systems on chip (SoCs) for microc...

296

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10bit 1Msps low power SAR ADC IP core

High performance, 8-bit resolution, 1-Msps sample rate Ultra Low Power Mixed-signal SAR ADC IP Core Node available in 95nm. Leading edge systems on ch...

297

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915MHz - 930MHz RPA12C Single stage low power low current PA

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298

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12-bit 1-channel up to 1 MSPS low power SAR ADC

055GF_ADC_02 is a low power 12-bit 1-channel ADC that uses a SAR architecture. The block consists of SAR ADC core and bias block The ADC settings allo...

299

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12-bit 1-channel up to 100kSPS low power SAR ADC

130GF_ADC_01 is a 12 bit, 1-channel, low power SAR ADC with sampling rates up to 100 kSPS. The ADC has two operating modes: single-shot conversion a...

300

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12-bit 1Msps Very low power SAR ADC silicon proven in 28nm

This is a 12-bit Successive Approximation Analog-to-Digital Converter (ADC) that operates up to 1MS/s. The ADC has excellent linearity with a small fo...

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