701 5.0

OTP One Time Programmable IP SIL180 Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...

702 5.0

OTP One Time Programmable IP Silterra 160HV Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...

703 5.0

OTP One Time Programmable IP SMIC 153nm Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...

704 5.0

OTP One Time Programmable IP SMIC 28HV Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...

705 5.0

OTP One Time Programmable IP SMIC 55HV Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...

706 5.0

OTP One Time Programmable IP SMIC130 Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...

707 5.0

OTP One Time Programmable IP XMC 55LL Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/40/28 nm). The require...

708 5.0

Sub-GHz 330 to 470 MHz Ultra Low Power Transceiver IP The ShortLink Sub-GHz Transceiver RF IP 'SL55S_Sub1GHzTRX_1' is a complete mixed signal RF IP for the 330 to 470 MHz frequency bands. Designed for hig...

709 5.0

DVB-RCS2 Turbo Decoder and Encoder IP Core On the transmitter side, the turbo-phi encoder architecture is based on a parallel concatenation of two double-binary Recursive Systematic Convolution...

710 5.0

DVB-S2X Wideband LDPC BCH Decoder IP Core The DVB-S2X Wideband LDPC Decoder is a powerful FEC core decoder for Digital Video Broadcasting via Satellite. It implements extensions to the DVB-S2 ...

711 5.0

DVB-T2 Demodulator and LDPC/ BCH Decoder IP Core The demodulator is designed to be used together with an RF tuner, and an analog to digital converter. The system has an internal state machine to cont...

712 5.0

NVME Host IP The new NVME-HOST-IP of Logic Design Solutions enables now random access in addition to the existing sequential access and multi-user access. FAT32 fi...

713 5.0

EXFAT IP Soft Core for NVMe The EXFAT IP Soft Core for NVMe supports any disk size and enables to reach the same speed as in raw format. One directory is created for each recordi...

714 4.0

18-bit Sigma Delta Stereo Audio Analog-to-Digital Converter IP in TSMC 28nm AD18SD28HPC is a complete low-cost stereo analog to digital converter for digital audio applications. The ADC comprises of a continuous time sigma del...

715 4.0

ECDSA IP The ECDSA IP is specifically designed for elliptic curve cryptography (ECC) using the ANSI X9.63 secp256k1 Koblitz curve. This cutting-edge ECDSA I...

716 4.0

DDI Scaler IP - BSCALE BTREE’s BSCALE enlarges or reduces the input video to fit the panel size. Polynomial Interpolation (PI) is the basic algorithm, and also various metho...

717 4.0

DDI Scaler IP - MSCALE BTREE’s MSCALE enlarges the input video to fit the panel size. Bi-Linear interpolation is the basic algorithm, and also various methods such as sharpn...

718 4.0

DDR3/DDR4 IP solution with high performance and low power With sophisticated architecture and advanced technology, KNiulink provide DDR3/DDR4 IP solution with high performance and low power. KNiulink could o...

719 4.0

Reed Solomon Decoder IP Core A high performance, fully configurable Reed Solomon Decoder IP Core that is intended for use in a wide range of applications requiring forward error c...

720 4.0

Reed Solomon Encoder IP Core A high performance, fully configurable Reed Solomon Encoder IP Core that is intended for use in a wide range of applications requiring forward error c...

721 4.0

NIST FIPS-197 Compliant High Throughput Rate AES IP Core ntAES128 core implements the NIST FIPS-197 Advanced Encryption Standard and can be programmed to either encrypt or decrypt 128-bit blocks of data usin...

722 4.0

NIST FIPS-197 Compliant Ultra-Low Power AES IP Core ntAES8 core implements NIST FIPS-197 Advanced Encryption Standard. ntAES8 core can be programmed to encrypt or decrypt 128-bit blocks of data using a ...

723 4.0

PKCS IP The PKCS IP is specifically designed for RSA Laboratories' Public-Key Cryptography Standards (PKCS) series, specifically PKCS #5 v2.0. Also used for E...

724 4.0

Dual channel 12-bit, 4GS/s ADC IP for 5G in 8nm process ADIQ12B4G08NLL is a Dual channel 12-bit analog-to-digital converter (ADC) that operates up to 4.0 GS/s. This ADC samples wide bandwidth analog signals...

725 3.25

eTCAM (Embedded Ternary Content Addressable Memory) IP TCAM can search for data that matches the input in one cycle from all the information stored in the memory.If there are multiple matching data, it is ...

726 3.25

eTCAM (Embedded Ternary Content Addressable Memory) IP TCAM can search for data that matches the input in one cycle from all the information stored in the memory.If there are multiple matching data, it is ...

727 3.0

13.56MHz NFC Transceiver IP supports ISO14443 A and B, ISO15693, FeliCa ™ The IP is NFC Transceiver AFE which includes microcontroller and memories integration, power management unit, clock management unit, peripheral interf...

728 3.0

GDDR6 PHY IP for GF12LPP The UniIC GDDR6 PHY，subsequently referred to as the UNIIC_GD6PHY, is designed for performance and power efficiency, its target is to deliver industry...

729 3.0

AES IP Core Encryption and Decryption are fed with an input of 128 bits length and an initial key of one of the supported key lengths (128, 192 and 256). The AES...

730 3.0

AHB2APB Bridge IP Truechip's AHB2APB Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency...

731 3.0

AHB2APB Bridge IP Truechip's AHB2APB Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency...

732 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in GF 28SLP process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

733 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

734 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 55LP process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

735 3.0

Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 65GP process TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

736 3.0

Single Lane and Quad Lane 16Gbps PCIe4.0 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS PCIe GEN4.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

737 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in GF 28SLP process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol a...

738 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

739 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 55LP process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

740 3.0

Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 65GP process TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

741 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in GF 28SLP process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

742 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

743 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 55LP process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

744 3.0

Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 65GP process TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...

745 3.0

Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process TERMINUS-CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single &Quad-Lane PCI Express PHY that supports PCI Express protocol and...

746 3.0

Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 28HPC process TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

747 3.0

Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 65G process TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...

748 3.0

MIPI RFFE Master IP SmartDV’s MIPI RFFE (Radio Frequency Front-End) Master IP is a silicon-proven solution designed for high-speed, low-latency control of RF front-end co...

749 3.0

MIPI SPMI Slave IP SmartDV’s MIPI SPMI (System Power Management Interface) Slave IP is a silicon-proven solution tailored for efficient communication with power manageme...

750 3.0

Complete measurement analog front end (AFE) IP for single phase power metering in TSMC 40uLPeF METRO-PM-MFE-mono.11-HD-IVT_TSMC_40_uLPeF is a Mixed-signal (analog and digital) Virtual Component in TSMC 40uLPeF. It is comprised of a high resoluti...