1201 0.118

DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 40nm LP process Boosting voltage from 3.3V to 5V, 100mA driving capability, Pulse Width Modulator, UMC 40nm Logic LP/RVT Low-K process....

1202 0.118

DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 65nm SP process Boosting voltage from 3.3V to 5V, 100mA driving capability, Ivcca=200uA @ Idrive=0, Pulse Width Modulator, UMC 65nm SP/HVT Logic Low-K process....

1203 0.118

DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 90nm SP process Boosting voltage from 3.3V to 5V, 100mA driving capability, Ivcca=200uA @ Idrive=0mA, Pulse Width Modulator, UMC 90nm SP/RVT Low-K process....

1204 0.118

DC-DC IP, Input: 3.3V, Output: 5V/50mA, HJTC 0.18um eFlash/G2 process PWM charge pump with internal soft start function. The input voltage is 3.3V. The output voltage is 5V with 50mA driving, HJ 0.18um eFlash process....

1205 0.118

DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.153um MS process Pulse Width Modulation, boosting voltage from 3.3V to 5V/50mA driving capability, Ivcca=140uA@Idrive=0, UMC 0.153um Logic/Mixed-Mode process....

1206 0.118

DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.18um G2 process Pulse width modulation, boosting voltage from 3.3V to 5V, 50mA driving capability, Ivcca=140uA @ Idrive=0....

1207 0.118

DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.25um Logic process Pulse width modulation, boosting voltage from 3.3V to 5V, 50mA driving capability, Ivcca=150uA @ Idrive=0....

1208 0.118

DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 65nm LL process DC-DC Power converter, Input:3.0V~3.6V, output:5V, 50mA loading, UMC 65nm LL/RVT Low_K process....

1209 0.118

DC-DC IP, Input: 5V, Output: 3.3V/300mA, UMC 0.11um HS/AE process 5.0V to 3.3V high efficiency converter with 300mA driving capability PWM Regulator, UMC 0.11um 1.2V/3.3V HS/AE (AL Advanced Enhancement) Logic process...

1210 0.118

DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.2V/50mA, UMC 0.13um HS/FSG process 3.3V to 1.2V high efficiency converter with 50mA driving capability, PWM Regulator, UMC 0.13um HS/FSG Logic process....

1211 0.118

DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.8V/150mA, with soft-start, UMC 0.13um LL/FSG process 3.3V to 1.8V high efficiency converter with 150mA driving capability, PWM Regulator, UMC 0.13um LL Logic/FSG process....

1212 0.118

DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.8V/200mA, with soft-start, UMC 0.13um HS/FSG process 3.3V to 1.8V high efficiency converter with 200mA driving capability PWM Regulator, UMC 0.13um HS/FSG Logic process....

1213 0.118

DC-DC IP, Step-up PWM Regulator, Input: 3.0V - 3.6V, Output: 5V/100mA, with soft-start, UMC 0.13um HS/FSG process PWM controller with soft start function for DC to DC boost converter, UMC 0.13um HS/FSG Logic process....

1214 0.118

PCI Express Differential Buffer IP, Single - Ended, UMC 90nm SP process 100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process....

1215 0.118

PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 55nm SP process PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process....

1216 0.118

PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 90nm SP process PCI-Express II PHY, UMC 90nm SP/RVT Low-K process....

1217 0.118

PCI Express Gen2 PHY IP, PCIe Gen-2, 4 Lanes, UMC 90nm SP process 4x lane PCI Express Gen II PHY, UMC 90nm SP/RVT Low-K Logic process....

1218 0.118

PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.13um HS/FSG process PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY with Low Power feature, UMC 0.13um HS/FSG Logic process....

1219 0.118

PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY, UMC 0.18um GII Logic (RVT) process....

1220 0.118

PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY, UMC 0.18um GII Logic (RVT) process....

1221 0.118

PCI-X Controller IP, PCIX 1.0b, Soft IP PCI-X 1.0b device/host bridge controller....

1222 0.118

PCIe Controller IP, PCIe Gen-2 with the AHB interface, x1 Lanes, Soft IP PCI Express Gen 2 Endpoint Controller. Support single-function, virtual channel and single lane....

1223 0.118

PCIe Controller IP, PCIe Gen-2 with the AXI interface, x4 Lanes, Soft IP PCIe Gen2 x4 Lane Endpoint Controller....

1224 0.118

SD Host Controller IP, SD host spec. v3.0, SDIO spec. v2.0, MMC spec. v4.3, Supports UHS50/UHS104 card, Soft IP SD host controller wih ahb interface, compliant with the SD Host Controller Standard Specification Version 3.00....

1225 0.118

DDR DLL (All Digital) IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...

1226 0.118

DDR DLL IP, 100MHz - 200MHz, Output: 13.5% - 36.6% Delay, UMC 0.11um HS/AE process DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhanceme...

1227 0.118

DDR DLL IP, 100MHz - 400MHz, Output: 25% Delay, UMC 0.13um HS/FSG process DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.13um HS/FSG process....

1228 0.118

DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/AE process DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic ...

1229 0.118

DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/FSG process DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/RVT Logic process....

1230 0.118

DDR DLL IP, Input: 100MHz - 150MHz, Output: 100MHz - 150MHz, UMC 0.18um G2 process Input 100M-150MHz, output 100M-150MHz, DDR DLL, UMC 0.18um GII Logic process....

1231 0.118

DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.13um HS/FSG process Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.13um HS/FSG Logic process....

1232 0.118

DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.15um SP process Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.15um SP Logic process....

1233 0.118

DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.162um LL process Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.162um Logic process....

1234 0.118

DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz -200MHz, UMC 0.18um G2 process Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.18um GII Logic process....

1235 0.118

DDR DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 65nm SP process Input 100-400MHz, output 100-400MHz, DDR2 DLL, UMC 65nm SP/RVT Low-K Logic process....

1236 0.118

DDR DLL IP, Input: 192MHz - 400MHz, Output: 96MHz - 200MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process UMC 0.13um HS/FSG process DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage....

1237 0.118

DDR DLL IP, Input: 200MHz - 333MHz, Output: 200MHz - 333MHz, UMC 90nm SP process Input 200-333MHz, output 200-333MHz, DDR2 DLL, UMC 90nm SP/RVT Low-K Logic process....

1238 0.118

DDR DLL IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, UMC 55nm SP process Input 200-400MHz, output 200-400MHz, DDR2 DLL, UMC 55nm SP Low-K Logic process....

1239 0.118

DDR DLL IP, Input: 333MHz - 667MHz, Output: 333MHz - 667MHz, UMC 90nm SP process Input 333M-667MHz, output 333M-667MHz, DDR2/3 Multi-phase DLL, UMC 90nm SP/RVT Low-K Logic process....

1240 0.118

DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process It is a UMC 0.13um HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller usage....

1241 0.118

DDR DLL IP, Input: 66MHz - 133MHz, Output: 66MHz - 133MHz, UMC 0.13um HS/FSG process Input 66M-133MHz, output 66M-133MHz, DDR DLL, UMC 0.13um HS/FSG Logic process....

1242 0.118

DDR DLL IP, Input: 66MHz - 200MHz, Output: 66MHz - 200MHz, UMC 90nm SP process Input 66M-200MHz, output 66M-200MHz, DDR DLL, UMC 90nm SP/RVT Low-K Logic process....

1243 0.118

DDR DLL IP, Input: 80MHz - 320MHz, Output: 6.25%-50% Delay, UMC 55nm SP process Input 80-320MHz, output 6.25%~50% delay, 80-320MHz, DDR2 DLL, UMC 55nm SP/RVT Low-K Logic process....

1244 0.118

DDR2/3 Controller IP, DDR2/3 controller with DFI 2.1 interfaces, Support DDR1/DDR2/DDR3 SDRAM, Soft IP DDR2/3 Combo SDRAM Controller....

1245 0.118

Memory Controller IP, Memory Stick controller, Soft IP Memory Stick host controller with AHB Bus....

1246 0.118

Memory Controller IP, NAND Flash memory Host controller, Soft IP NAND flash host controller with AHB interface, it supports SLC and MLC NAND flash....

1247 0.118

General Purpose IO IP, 1.8V BOAC EMMC I/O, Support built-in Pull-Up / Pull-Down , UMC 28nm HLP process UMC 28nm Logic and Mixed-Mode HLP/RVT process 1.8V BOAC EMMC IO Cell Library (with customized PU/PD function)....

1248 0.118

General Purpose IO IP, 1.8V Operations, UMC 0.18um eHV process UMC 0.18um Embedded High-Volatge process,1.8V IO Cells....

1249 0.118

General Purpose IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.153um MS process UMC 0.153um Mixed-Mode/Logic process mini IO (blown up version of 0.18u Mini-IO)....

1250 0.118

General Purpose IO IP, 1.8V/2.5V/3.3V Operations, UMC 90nm SP process UMC 90nm SP/RVT Low-K process 2.5V over-drive 3.3V GOX52 process IO....