Design & Reuse
4652 IP
2151
0.118
PCI Express Differential Buffer IP, Single - Ended, UMC 90nm SP process
100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process....
2152
0.118
PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 55nm SP process
PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process....
2153
0.118
PCI Express Gen2 PHY IP, PCIe Gen-2, 1 Lanes, UMC 90nm SP process
PCI-Express II PHY, UMC 90nm SP/RVT Low-K process....
2154
0.118
PCI Express Gen2 PHY IP, PCIe Gen-2, 4 Lanes, UMC 90nm SP process
4x lane PCI Express Gen II PHY, UMC 90nm SP/RVT Low-K Logic process....
2155
0.118
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.13um HS/FSG process
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY with Low Power feature, UMC 0.13um HS/FSG Logic process....
2156
0.118
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY, UMC 0.18um GII Logic (RVT) process....
2157
0.118
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.18um G2 process
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY, UMC 0.18um GII Logic (RVT) process....
2158
0.118
PCI-X Controller IP, PCIX 1.0b, Soft IP
PCI-X 1.0b device/host bridge controller....
2159
0.118
PCIe Controller IP, PCIe Gen-2 with the AHB interface, x1 Lanes, Soft IP
PCI Express Gen 2 Endpoint Controller. Support single-function, virtual channel and single lane....
2160
0.118
PCIe Controller IP, PCIe Gen-2 with the AXI interface, x4 Lanes, Soft IP
PCIe Gen2 x4 Lane Endpoint Controller....
2161
0.118
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process.
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process....
2162
0.118
PCIe Gen4 x8 Lane Endpoint Controller
PCIe Gen4 x8 Lane Endpoint Controller...
2163
0.118
SD Host Controller IP, SD host spec. v3.0, SDIO spec. v2.0, MMC spec. v4.3, Supports UHS50/UHS104 card, Soft IP
SD host controller wih ahb interface, compliant with the SD Host Controller Standard Specification Version 3.00....
2164
0.118
SD host controller wih ahb interface, compliant with the SD Host Controller Standard Specification Version 2.00
SD host controller wih ahb interface, compliant with the SD Host Controller Standard Specification Version 2.00...
2165
0.118
ID PAD of OTG USB2.0 ; XIP 55LP/RVT LowK Logic Process
ID PAD of OTG USB2.0 ; XIP 55LP/RVT LowK Logic Process...
2166
0.118
ADC controller for Faraday internal use.
ADC controller for Faraday internal use....
2167
0.118
DDR DLL (All Digital) IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...
2168
0.118
DDR DLL IP, 100MHz - 200MHz, Output: 13.5% - 36.6% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhanceme...
2169
0.118
DDR DLL IP, 100MHz - 400MHz, Output: 25% Delay, UMC 0.13um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.13um HS/FSG process....
2170
0.118
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic ...
2171
0.118
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/RVT Logic process....
2172
0.118
DDR DLL IP, Input: 100MHz - 150MHz, Output: 100MHz - 150MHz, UMC 0.18um G2 process
Input 100M-150MHz, output 100M-150MHz, DDR DLL, UMC 0.18um GII Logic process....
2173
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.13um HS/FSG process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.13um HS/FSG Logic process....
2174
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.15um SP process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.15um SP Logic process....
2175
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.162um LL process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.162um Logic process....
2176
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz -200MHz, UMC 0.18um G2 process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.18um GII Logic process....
2177
0.118
DDR DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 65nm SP process
Input 100-400MHz, output 100-400MHz, DDR2 DLL, UMC 65nm SP/RVT Low-K Logic process....
2178
0.118
DDR DLL IP, Input: 192MHz - 400MHz, Output: 96MHz - 200MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG process DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage....
2179
0.118
DDR DLL IP, Input: 200MHz - 333MHz, Output: 200MHz - 333MHz, UMC 90nm SP process
Input 200-333MHz, output 200-333MHz, DDR2 DLL, UMC 90nm SP/RVT Low-K Logic process....
2180
0.118
DDR DLL IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, UMC 55nm SP process
Input 200-400MHz, output 200-400MHz, DDR2 DLL, UMC 55nm SP Low-K Logic process....
2181
0.118
DDR DLL IP, Input: 333MHz - 667MHz, Output: 333MHz - 667MHz, UMC 90nm SP process
Input 333M-667MHz, output 333M-667MHz, DDR2/3 Multi-phase DLL, UMC 90nm SP/RVT Low-K Logic process....
2182
0.118
DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
It is a UMC 0.13um HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller usage....
2183
0.118
DDR DLL IP, Input: 66MHz - 133MHz, Output: 66MHz - 133MHz, UMC 0.13um HS/FSG process
Input 66M-133MHz, output 66M-133MHz, DDR DLL, UMC 0.13um HS/FSG Logic process....
2184
0.118
DDR DLL IP, Input: 66MHz - 200MHz, Output: 66MHz - 200MHz, UMC 90nm SP process
Input 66M-200MHz, output 66M-200MHz, DDR DLL, UMC 90nm SP/RVT Low-K Logic process....
2185
0.118
DDR DLL IP, Input: 80MHz - 320MHz, Output: 6.25%-50% Delay, UMC 55nm SP process
Input 80-320MHz, output 6.25%~50% delay, 80-320MHz, DDR2 DLL, UMC 55nm SP/RVT Low-K Logic process....
2186
0.118
DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...
2187
0.118
DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...
2188
0.118
DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process
DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process...
2189
0.118
DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process
DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process...
2190
0.118
DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process
DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process...
2191
0.118
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process...
2192
0.118
DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process
DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process...
2193
0.118
DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process
DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process...
2194
0.118
DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process
DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process...
2195
0.118
DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process
DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process...
2196
0.118
DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process
DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process...
2197
0.118
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process...
2198
0.118
DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process
DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process...
2199
0.118
DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process
DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process...
2200
0.118
DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process
DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process...