Design & Reuse
Catalog of SIP Cores
System on Chip design resources
4905 IP
4851
0.0
DP1.2 Transmitter PHY_40nm
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
4852
0.0
DP1.4 Receiver Controller
This document describes the low power Innosilicon DP 1.4 Receiver controller, which is fully compliant with DP 1.4 specification and eDP 1.4 standard....
4853
0.0
DP1.4 TX PHY
Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...
4854
0.0
LPDDR2 PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR2 PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devi...
4855
0.0
LPDDR3/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR3/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SD...
4856
0.0
LPDDR3/2/DDR3/3L Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR2/3/DDR3/3L COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compa...
4857
0.0
LPDDR3/2/DDR3/3L/2 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR3/2/DDR3/3L/2 COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC com...
4858
0.0
LPDDR4X, LPDDR4, DDR4, LPDDR3 Combo PHY & Controller
The INNOSILICON DDR IPTM Mixed-Signal LPDDR4/4X/DDR4/LPDDR3 PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compat...
4859
0.0
LPDDR4X/4/3/DDR4/3/3L PHY + Controller
INNOSILICON™ LPDDR4X/4/3/DDR4/3/3L Combo IP is a customizable Mixed-Signal DDR memory interface suite. The Combo IP provides turnkey physical interfac...
4860
0.0
Specialty SSTL IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process true 2.5V SSTL2 IO cells....
4861
0.0
CPU IP - Follows the RVA23 Profile, supports RVV1.0 and supports all extensions of Vector Crypto
StarFive Dubhe-83 CPU IP features a 10+ stage pipeline, 3-issue, and out-of-order pipeline, follows the RVA23 Profile, supports RV64GCBVH, supports RV...
4862
0.0
MRDIMM DDR5 & DDR5/4 PHY & Controller
INNOSILICON™ DDR5 IP includes the MRDIMM DDR5 PHY and DDR5/4 Combo PHY and corresponding controllers for ICs requiring access to JEDEC compatible SDRA...
4863
0.0
Process/Voltage/ Temperature Sensor
INNOSILICON™ PVT Sensor IP is designed for on-chip monitoring of processes, voltage, and temperature variations. It is a critical component in modern ...
4864
0.0
ARP/ICMP Protocol for Ethernet
The CT1006-XGARP/ICMP block adds RTL-hardened functions for ICMP and ARP to any FPGA application. The all-RTL block includes part of the ARP protoc...
4865
0.0
ARTIEYE Driver Monitoring System (DMS) Technology Suite
Driver Monitoring Systems (DMS) reduce the number of car accidents related to driver drowsiness and distraction, and make roads safer for everyone. DM...
4866
0.0
USB 2.0/1.1 PHY (6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm)
USB 2.0 PHY M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power consumptio...
4867
0.0
USB BCK Technology (22nm, 40nm, 55nm, 110nm)
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK function. M31’s patented BCK (Bu...
4868
0.0
USB Type-C and Power deliver Controller
USB Type-C and Power deliver Controller...
4869
0.0
Pseudo 2 Port High-Current Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option
Pseudo 2 Port High-Current Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...
4870
0.0
HSIC PHY
The Innosilicon HSIC PHY is fully compliant with the High-Speed Inter-Chip Supplement to the USB 2.0 Specification. By stripping off all the legacy US...
4871
0.0
PSRAM PHY
The INNOSILICON DDR IPTM Mixed-Signal PSRAM PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible PSRAM devic...
4872
0.0
PSRAM/RPC PHY & Controller
INNOSILICON™ PSRAM IP consists of a configurable PHY and RPC PHY and a controller. It provides the physical interface solutions for ICs requiring acce...
4873
0.0
JTAG 2-Wire to 4-Wire Adapter
The OT4001_cjtag is an adapter which permits legacy IEEE 1149.1 ports to communicate as an IEEE 1149.7 2-wire OScan1 cJTAG port. A simple update to a ...
4874
0.0
StarFive -RISC-V design services and training
Founded in 2018, StarFive is a Chinese local high-tech company with independent intellectual properties. As the leader of the RISC-V software and hard...
4875
0.0
LTE UE PHY layer
The PHY baseband covers all Synchronization Signals, downlink and uplink Physical Channels, libraries, algorithms integrated with cross-functional log...
4876
0.0
LTE UE Protocol Stack HW (Arm, Cortex A8)
Mymo offers 3GPP LTE Release-9 UE FDD and TDD UE Protocol Stack on Arm hardware . The Integrated solution of MAC-RLC-PDCP-RRC-NAS-TCP-IP with several ...
4877
0.0
LTE UE Protocol Stack Software
Mymo offers 3GPP LTE Release-9 UE FDD and TDD UE Protocol Stack software. The software is in ANSI C ported at RT-Linux kernel level ideally suited for...
4878
0.0
Dual Port High-Current SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option
Dual Port High-Current SRAM Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...
4879
0.0
Successive Approximation ADC_2M10b
Innosilicon SARADC IP is a small-sized, low power analog to digital converter with input channels. The converter is a charge-redistribution successive...
4880
0.0
Successive Approximation ADC_2M12b
Innosilicon SAR-ADC IP is a small-size, low power analog to digital converter. The converter is a charge-redistribution successive approximation ADC. ...
4881
0.0
Successive Approximation ADC_3M10b
Innosilicon SARADC IP is a small-sized, low power analog to digital converter with input channel and Standard I/O multiplexed. The converter is a char...
4882
0.0
Nuclei N100: Very tiny area 2-stage-pipeline processor for embedded applications
Entry-level 32-bit RISC-V core, one of the world's smallest RISC-V cores. Optimized for ultra-low power consumption and minimal area, targeting cost-s...
4883
0.0
Nuclei N200: Ultra-low-power 2-stage-pipeline processor for embedded applications
Mid-range 32-bit RISC-V core, the world's first general-purpose MCU based on RISC-V. Balancing power, performance and area, comparable to ARM Cortex-M...
4884
0.0
Nuclei N300: Low-power 3-stage-pipeline processor with DSP/FPU capable for embedded applications
High-performance 32-bit RISC-V core, Nuclei's most widely adopted, feature-rich embedded core. Suitable for complex real-time embedded applications, w...
4885
0.0
Nuclei N600(SMP): 32-bit high-efficiency 6-stage-pipeline processor with DSP/FPU capable for embedded and real-time applications
32-bit high-efficiency multi-core processor without MMU, comparable to ARM Cortex-R4/R5, based on the Nuclei 600 Series architecture, supporting 2–4 c...
4886
0.0
Nuclei NI1000: AI-optimized high-performance processor with advanced vector extension (up to 4096-bit) for high-end AI and HPC applications
64-bit high-end high-throughput RISC-V core, belonging to Nuclei 1000 series with out-of-order execution architecture. It adopts 2-wide decode design,...
4887
0.0
Nuclei NI900: AI-optimized high-performance processor with advanced vector extension (up to 1024-bit) for AI applications
64/32-bit high-performance RISC-V core, supporting single-core and cluster SMP configurations. Equipped with powerful VPU, FPU and crypto accelerators...
4888
0.0
Nuclei NS100: 32-bit ultra-low-power 2-stage-pipeline secure processor for EAL 5+ secure embedded applications
32-bit ultra-low-power RISC-V core, designed for ultra-low-power MCU, IoT and other low-power applications. A competitive rival to ARM SC000, with mi...
4889
0.0
Nuclei NS300: 32-bit low-power 3-stage-pipeline secure processor for EAL 5+ secure embedded applications
32-bit security-enhanced low-power RISC-V core, evolved from Nuclei N300 with enhanced security features. A competitive rival to ARM SC300/M35P, combi...
4890
0.0
Nuclei U600(SMP): 32-bit high-efficiency 6-stage-pipeline processor (with MMU) for Linux-capable applications
32-bit high-efficiency RISC-V core with MMU, belonging to Nuclei 600 Series. Comparable to ARM Cortex-A5/A7, supporting 32-bit Linux system, balancing...
4891
0.0
Nuclei U900(SMP): 32-bit high-efficiency 9-stage-pipeline processor (with MMU) for Linux-capable applications
32-bit high-performance RISC-V core with MMU, belonging to Nuclei 900 Series. Comparable to ARM Cortex-A7/A9, supporting 32-bit Linux system, dual-iss...
4892
0.0
Nuclei UX600(SMP): 64-bit high-efficiency 6-stage-pipeline processor (with MMU) for Linux-capable applications
Entry-level 64-bit high-efficiency RISC-V core with MMU, belonging to Nuclei 600 Series. Comparable to ARM Cortex-A35/A53, supporting 64-bit Linux sys...
4893
0.0
Nuclei UX900(SMP): 64-bit high-efficiency 9-stage-pipeline processor (with MMU) for Linux-capable applications
64-bit high-performance RISC-V core with MMU, belonging to Nuclei 900 Series. Comparable to ARM Cortex-A35/A53/A55, dual-issue execution, supporting 6...
4894
0.0
Audio Codec
INNOSILICON™ Audio Codec IP is a low power, high resolution, stereo audio solution which leverages Sigma-Delta noise-shaping technology. The ADC, DAC,...
4895
0.0
PUF Security
A physical unclonable function, or PUF, is a "digital fingerprint" that serves as a unique identity for a semiconductor device such as a microprocesso...
4896
0.0
eUSB2 PHY
The industry’s most advanced process nodes do not support 3.3V signaling and 5V tolerance as required by the USB 2.0 specification. 3.3V signaling was...
4897
0.0
JVC_4K Adoptive Scaler + Super Resolution - Convert Full-HD to High quality 4k2k with super resolution technology
JVC s 4k2k Super Resolution IP is now available for licensing. It offers dramatically less jaggy and Full-HD to 4k2k up-conversion with high performan...
4898
0.0
LVDS RX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...
4899
0.0
LVDS TX Combo TTL PHY
Innosilicon LVDS implements LVDS TIA/EIA protocol. Normally, Innosilicon LVDS contains four 7-bit parallel-load serial-out shift registers, a 7X clock...
4900
0.0
LVDS TX PHY & Controller
Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...