Catalog of SIP Cores
System on Chip design resources
System on Chip design resources
June 4, 2026 -
The software is designed to cut RTL validation from about five weeks to less than a day using automated simulation and formal flows.
At Computex 2026, Cadence announced the industry’s first fully autonomous virtual agentic AI design engineer, extending the ChipStack AI Super Agent to Level-5 autonomy. Built on Cadence’s AI-driven electronic design automation (EDA) portfolio with NVIDIA Nemotron models, and secured by NVIDIA OpenShell runtime, the new agentic capabilities enable customers to run dynamic simulations in automated workflows. At NVIDIA, 1000s of engineers are using billions of compute hours per year to run millions of tests to verify their designs. Each engineer will use ChipStack agents to run hundreds of dynamic simulations with Cadence Xcelium Logic Simulation and Jasper Formal Verification, delivering over 40X faster RTL validation cycles and reducing a typical five-week verification loop to less than a day, dramatically accelerating the validation of complex semiconductor designs.