Catalog of SIP Cores
System on Chip design resources
System on Chip design resources
June 11, 2026 -
RISC-V Summit Europe is coming to Bologna, Italy, with a program that reflects just how far the ecosystem has come since we gathered in Paris a year ago. Taking place June 8–12 2026 at the Palazzo dei Congressi, the summit unites members, manufacturers, researchers, public institutions, academics and students, all helping to nurture the RISC-V open standard instruction set architecture (ISA).
There is something very fitting about the RISC-V ecosystem gathering in Bologna. The city’s university, the oldest in the Western world, was founded in 1088 by students who wanted to take their education into their own hands. Over 900 years later, that same instinct surfaced at University of California Berkeley, where students and staff created RISC-V in 2010: an ISA deliberately designed to put the ability to learn and build silicon chips into anyone’s hands.