Andes Technology Introduces Next-Generation Andes Automated Custom Extension to Simplify Domain-Specific RISC-V Processor Innovation

November 10, 2026 -

Andes announced the latest generation of its Andes Automated Custom Extension (ACE), enhanced with COPILOT V7, enabling SoC designers to accelerate domain-specific workloads more efficiently!

HSINCHU, Taiwan – Andes Technology (TWSE: 6533), the leading supplier of high-performance, low-power 32-bit and 64-bit RISC-V processor IP and a Founding Premier member of RISC-V International, today announced the latest generation of its Andes Automated Custom Extension (ACE), an advanced development framework that dramatically simplifies the creation of application-specific RISC-V instructions. The enhanced version of its tool COPILOT V7 enables SoC designers to rapidly accelerate domain-specific workloads while eliminating much of the complexity traditionally associated with CPU customization.

As AI, networking, storage, automotive, and edge computing applications continue to demand greater performance and energy efficiency, processor differentiation has become increasingly important. While the open RISC-V ISA enables custom instruction extensions, implementing them typically requires extensive processor design expertise and significant software toolchain development. ACE framework removes these barriers by automating the integration of custom instructions into CPU RTL, Compiler and Simulator through COPILOT.

The latest COPILOT has been used widely in scenarios below:

• Low latency control to external HW blocks such as NPU with ACE custom ports (ACP)
• Special AI or DSP computation instructions such as exp(x), sin(x), and cos(x)
• More data type support for fast-growing AI need such as fp8 and int4

COPILOT V7 introduced several key features, including:

• ACE_RVV: support customized RISC-V vector (RVV) instructions by adding ACE capability on top of the power RVV SIMD Engine.
• FRF Access: allow ACE logic to access floating point registers
• 64-bit ACE instructions: double the bits available for encoding custom instructions
• Heterogeneous ACE instructions: allow each core in the same cluster to instantiate only ACE instructions it needs instead of all ACE instructions to save hardware (E.g. some have the powerful exp(x) instruction while others don’t)
• Quad widening and narrowing support: allow ACE_RVV instructions to do quad data format conversion.

Also, due to strong customer requests, the ACE support is being extended to the whole CPU family, from the compact 3-stage MCU level D23 to out-of-order application processor AX66.

Andes has offered custom instructions on AndesCore™ processors for 20 years, with many loyal customers. Here are a few examples.

“By integrating Andes’ RISC-V cores and ACE technology into our architecture, we’ve built a flexible and scalable platform that meets the performance, power, and cost demands of AI applications at the edge and in the data center.” – Phison Electronics

“The cores are single issue, in-order cores, with a five-stage pipeline (AX25-V100, from Andes Technology), and are heavily customized to suit the functionalities needed. The set of customizations includes custom interfaces, custom registers, custom instructions, and custom exceptions.” – “MTIA: First Generation Silicon Targeting Meta’s Recommendation Systems”, ISCA 2023.

“Fractile will integrate Andes Technology’s high-performance RISC-V vector processor with its own groundbreaking in-memory computing architecture via ACE.” – Fractile  

“Every SoC design team has unique algorithms that differentiate their products,” said Dr. Charlie Su, President and CTO of Andes Technology. “Our latest ACE framework makes it easier than ever for customers to transform their algorithms into custom processor instructions. Instead of spending months modifying CPU RTL and software tools, designers can focus entirely on their application innovations while COPILOT automatically builds the surrounding processor infrastructure. This dramatically shortens development cycles for instruction creation and allows customers to fully leverage the flexibility of the RISC‑V architecture.”

By integrating custom instructions directly into native CPU execution, ACE eliminates the latency, software overhead, and memory bottlenecks common to traditional memory-mapped coprocessors. Combined with background processing that enables true parallel hardware acceleration, ACE delivers unmatched system throughput and sets a new efficiency standard for custom domain-specific compute.

About Andes Technology

As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is driving the global adoption of RISC-V. Andes’ extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters. With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices. Over 20 billion Andes-powered SoCs are driving innovations globally. Discover more at www.andestech.com.