Catalog of SIP Cores
System on Chip design resources
System on Chip design resources
August 3, 2026 -
As artificial intelligence expands beyond data centers and into edge devices, autonomous systems, industrial equipment, and even spacecraft, power efficiency is becoming one of the industry’s most important challenges.
While AI models continue to grow in capability, conventional computing architectures still rely on constant movement of data between memory and processors. This data movement consumes energy, increases latency, and creates system-level bottlenecks, particularly in environments where power and thermal budgets are limited.
To address this challenge, researchers are increasingly investigating In-Memory Computing (IMC) architectures that bring computation closer to where data resides. By performing computation within memory arrays, such architectures can significantly improve efficiency while reducing latency and system complexity.
ReRAM is particularly well suited to IMC research because the same memory cells used to store neural-network weights can also participate in analog computation within crossbar arrays. This reduces data movement while allowing many multiply-accumulate operations to occur in parallel, making the architecture attractive for energy-constrained AI applications.
Recently, a U.S. based company developing radiation-tolerant AI hardware used Weebit ReRAM to develop and evaluate a next-generation IMC AI accelerator. The work was part of a project focused on developing low-power AI inference capabilities for harsh-environment applications.
The project explored neural-network operations implemented directly on ReRAM-based compute arrays. Researchers were able to characterize memory behavior, evaluate compute-in-memory techniques, and benchmark the architecture against GPU- and FPGA-based implementations of the same inference workload.