Andes and Imperas Partner to Deliver Models and Virtual Platforms for Andes RISC-V Cores

Imperas Provides Virtual Prototype Software Solutions and Models for V5 AndesCoreTM N25 and NX25 Processors

Oxford, United Kingdom, November 20th, 2017 - Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, and Andes Technology Corporation, today announced their partnership to provide Open Virtual Platforms (OVP) models, virtual platforms and software solutions for Andes next-generation processors, based on the RISC-V architecture.

The momentum for RISC-V is accelerating, and Andes is the first established CPU intellectual property (IP) vendor to offer a RISC-V processor for licensing, delivering the V5 AndesCore™ N25 and NX25 IPs. Andes designs low-power CPU cores for a full range of embedded electronics products, including low-cost embedded applications, data centers, connected, smart and green applications, machine-learning accelerators, communications, security, IoT, and consumer applications.

Imperas is the leading provider of RISC-V processor models. Imperas models and virtual prototype solutions include both the NX25 64-bit and N25 32-bit cores, and are available now from Imperas and the Open Virtual Platforms (OVP) website. The AndeStar™ V5 is the superset of RISC-V instruction set, whose baseline comprises roughly 60 instructions, with Andes-specific performance enhancement extensions.

Charlie Hong-Men Su, Ph.D., Andes Technology CTO and Senior VP, commented, "The Imperas virtual platform solutions for software development, debug and test, along with their open-source models, comprise an excellent methodology for development of embedded software for SoCs based on V5 AndesCore N25 and NX25 processors."

"“Support for Andes’ new low power RISC-V based 32-bit/64-bit CPU cores by Imperas, the leading commercial simulation offering, will accelerate adoption of RISC-V IP," said Simon Davidmann, president and CEO of Imperas.

Rick O’Connor, Executive Director, RISC-V Foundation, said, "A healthy RISC-V ecosystem is critical to the adoption of RISC-V processors. The open RISC-V ISA specifications make it easier for ecosystem companies like Imperas and Andes to collaborate. Tools such as the Imperas RISC-V models, virtual platforms and software solutions will improve time to market by enabling faster software development, simplifying debug and test, lowering costs and risks and delivering overall increased quality."

Imperas delivers a comprehensive environment for embedded software development, debug and verification for Andes N25 and NX25 processors, including open-source Fast Processor Models; extendable virtual platforms including cores and peripherals; high-performance simulation; analytical tools for hardware-dependent multicore software development, debug and test including OS-aware tools. The Extendable Platform Kits (EPKs) for Andes cores run FreeRTOS, and also support heterogeneous designs with mixtures of Andes processors and other vendors’ cores including application processors.

Video demos showing Imperas heterogeneous platforms with RISC-V based Andes N25 core OVP models running FreeRTOS are available here:

1. Simulating Andes RISC-V N25 running FreeRTOS and ARM Cortex-A15MPx4 running SMP Linux.
2. Multiprocessor debug of a platform including an Andes RISC-V N25 running FreeRTOS and ARM Cortex-A15MPx4 running SMP Linux.

Imperas will demonstrate models and virtual platforms for RISC-V designs, based on Andes cores, at the 7th RISC-V Workshop, November 28-30, 2017 in Milpitas California.

The new models of the Andes cores expand Imperas and OVP processor support to over 180 models across a wide variety of vendors. For the latest list of Imperas models, please see www.OVPworld.org.

About Andes Technology Corporation

Andes Technology Corporation was founded in Hsinchu Science Park, Taiwan in 2005 to develop innovative high-performance/low-power 32-bit/64-bit processor cores and its associated development environment to serve worldwide rapidly-growing embedded system applications. For more information, visit http://www.andestech.com/