Oakland, Calif. – December 12, 2017 – Averant Inc., the First In Formal™ leader in property verification of RTL designs for digital circuits, today announced the release of Solidify 6.5. Some of the highlights of this release are listed below.
- Machine learning inspired signal matching in SEC/CEC. The first step in equivalency checking is identifying candidate signals which are equal. Release 6.5 extends capabilities of prior releases with many new ideas including some inspired by statistical learning and machine learning technologies.
- Speed improvements, complete difficult problems, and better library support in CEC. Release 6.5 provides improved library support and several new techniques to improve speed and complete difficult problems.
- New usability features in clock crossing inspired by relational databases. Using ideas from relational databases, release 6.5 offers the users a variety of ways to view and analyze their clock domain crossing signals in the same way that the SQL database language allows for browsing and analyzing data.
Release 6.5 also contains improvement in property verification, coverage, debugging, GUI, PSL and SVA support.
"Release 6.5 was the result of close collaboration with our customers and made immediate impact on their verification challenges" commented Ramin Hojati, president of Averant. "This all happened while ideas from the rest of computer science were implemented in Solidify, enriching our development team and customers' experiences".
Release 6.5 is available for use immediately.
Averant Inc. is a privately held EDA firm specializing in formal verification of digital designs. Averant’s signature product is Solidify, a robust platform for property, protocol, and automatic design checks – all without the need for simulators or test vectors. Averant's tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, visit http://www.averant.com.