Catalog of SIP Cores
System on Chip design resources
System on Chip design resources
July 24, 2026 -
July 27-29, 2026, Long Beach Convention Center, Booth #1349
Who
True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) and computer aided design (CAD) software for the semiconductor, systems and electronics industries.
What
At the 63rd Design Automation Conference (DAC), TCI will showcase its powerful JSPICE™ Design Environment (JDE™) which has been used by True Circuits over the last 28 years to create complex analog and digital IP. TCI has announced its intention to offer JDE open source to form the foundation of a modern AMS development environment that unifies design generation, simulation, measurement, characterization, data analysis, and AI-assisted engineering into a single extensible environment. TCI will also showcase its complete line of high performance and general purpose analog and synthesizable PLL and DLL IP, as well as its innovative and flexible DDR PHY IP.
Following on announcements of JDE availability through a beta program over the last two years, TCI sees the immense value of putting JDE in the hands of the open source analog design community so users, content creators and service providers can freely use and contribute to this powerful design environment. The goal is to create a vibrant JDE ecosystem where work and ideas can be shared, problems solved and innovation unleashed to dramatically improve design quality and reduce design time.
True Circuits will offer daily JSPICE™ Design Environment (JDE™) presentations and demos highlighting the features and uses of this powerful design environment. We are glad to discuss how interested users, whether individuals, students or employees of companies, can start benefitting from and contributing to the open JDE ecosystem.
In addition to JDE, TCI will showcase its complete line of high performance and general purpose analog and synthesizable PLL and DLL IP, as well as its innovative and flexible DDR PHY IP. The high performance, silicon proven DDR PHY has fully automatic training managed by a light weight special purpose processor, and remarkable physical flexibility to adapt to each customer’s die floorplan and package.
The PHY supports LPDDR5, DDR4, LPDDR4, DDR3, and LPDDR3 protocols, and is available in a variety of TSMC processes. The availability of this silicon proven PHY means customers can now license a PHY with significant performance and features without all the implementation and timing closure hassles that are common with current DDR offerings. During the show, we will be giving short presentations and demos of our DDR PHY in action. This will be a great opportunity to ask questions and learn what makes a TCI DDR PHY hard macro one special piece of IP.
As always, we are happy to discuss your chip requirements and timing needs, and recommend the best PLL or DLL from our complete line of high performance and general purpose timing IP. These high quality, low-jitter PLL and DLL hard and soft macros are suited to a wide variety of interface standards and chip applications. They are pin-programmable, highly process tolerant, reusable and available for delivery in TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 5nm.
When and Where
Long Beach Convention Center, Long Beach, CA
Contacts
For more information about True Circuits' PLLs, DLLs, DDR PHYs and JDE™, please visit www.truecircuits.com.
For more information about the Design Automation Conference, please visit www.dac.com.
About JDE™
Digital design has become highly driven by software standards and abstraction. It has achieved impressive productivity gains and is poised to benefit from the use of AI. Analog and mixed-signal (AMS) design has not. Much of AMS design remains tied to schematics, fragile scripts, manual analysis, and knowledge that exists primarily in the heads of a few experienced engineers. With JDE, analog designers can be at least 10X more productive. Adding AI and building a community may increase that to 100X or more.
JDE replaces a company or designer-specific flow that is saddled with multiple data formats and ad hoc scripts with open engineering languages, APIs and shared data models that are easy to use and reuse. Much like digital verification, JDE has several layers of abstraction for measurement and analysis, and complete characterization frameworks.
JDE enables users to run massively parallel, mixed mode simulations, either locally or in the cloud, or both with unlimited simulator licenses. JDE supports SPICE, Verilog and Verilog-A. It does directed logic synthesis and includes sophisticated Statistical Timing Analysis (STA) that uses SPICE data for each subcircuit. A preprocessor compiles an expressive netlist generation language supporting process node parameterization, conditional generation, reusable libraries and programmable circuit generation. JDE is designed to support multiple commercial and open-source simulators through common interfaces.
About the JDE™ Ecosystem
The JDE open ecosystem allows engineering knowledge, not just software, to be shared. Characterization packages, measurement libraries, generators, verification suites, and AI agents can all build on common languages and shared data models. It will be easily accessible by a variety of users, from universities and businesses to individual designers, all providing content and services to make JDE the development environment of the future. The future of semiconductors lies with universities that attract and train engineering talent, and JDE is positioned to be their design environment of choice.
For more information about JDE, visit www.truecircuits.com/jspice.html.
For discussion about JDE and how to get started, contact Brian Gardner, V.P. of Business Development, True Circuits, Inc., bgardner@truecricuits.com.
About True Circuits Analog PLLs and DLLs
True Circuits offers a complete family of standardized and silicon-proven general purpose, clock generator, deskew, spread spectrum, IoT and Ultra PLLs, and multi-slave and multi-phase DLLs that spans nearly all performance points and features typically requested by ASIC, FPGA and SoC designers. These high quality, low-jitter PLL and DLL hard macros are suited to a wide variety of interface standards and chip applications. They are pin-programmable, highly process tolerant and reusable. They are also easy to integrate and are fully supported, so customers can reduce both design and silicon risks.
True Circuits PLLs support a wide range of frequencies, multiplication factors and functions over which they deliver optimal performance. TCI’s PLLs are available with ring-oscillator and LC-tank architectures, fractional-N division and frequency spreading for EMI reduction. TCI's DLLs are available in multi-slave and multi-phase versions and different sizes and form factors. They delay a set of signals by precise and adjustable fractions of a reference clock cycle independent of voltage and temperature and are ideal for high-speed DDR and ONFI interface applications. Customized PLL and DLL solutions are also available for specialized chip applications.
True Circuits PLLs and DLLs are available for immediate customer delivery in TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 5nm. For more information about True Circuits IP products, visit www.truecircuits.com/tci_technology.html and www.truecircuits.com/product_matrix.html.
About True Circuits DDR PHYs
The DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read gate and data eye timing are also continuously adjusted. Fully automatic training is managed by a light weight special purpose processor and includes multi-cycle write leveling and read gate training and also read/write data eye training, including PHY Vref and DRAM Vref settings.
The PHY employs a localized and optimized PHY-to-memory controller interface to ease timing closure. The circuitry in each pin is able to measure the data eye and jitter, and calculate flight delays. The PHY also includes a full speed read/write BIST, which tests the complete read and write paths of every pin simultaneously with pseudo-random data.
Remarkable physical flexibility allows the PHY to adapt to each customer's die floorplan and package constraints, yet is verified and delivered as a unit for easy timing closure with no assembly required. The PHY supports LPDDR5, DDR4, LPDDR4, DDR3 and LPDDR3, and is DFI 5.1 compliant. When combined with an appropriate DDR memory controller, a complete and fully-automatic DDR system is realized.
The True Circuits DDR PHY is silicon proven and available for customer delivery in a variety of TSMC processes from 40nm to 3nm. Interested customers can obtain more product information on the web at www.truecircuits.com/ddr_phy.html or by contacting True Circuits at sales@truecircuits.com.
About True Circuits
True Circuits develops and markets a broad range of industry leading PLLs, DLLs and DDR PHY hard macros for ICs for the semiconductor, systems and electronics industries. TCI's robust state-of-the-art circuits, methodical and proven design strategy, and close association with the world's leading foundries, IDMs, and design services companies allow the company to quickly and reliably create new and innovative designs in a variety of advanced process technologies. Over the last 28 years, True Circuits has distinguished itself as a technology leader in the timing IP space, and its PLLs and DLLs are used extensively around the world in its customers' products with production volumes well into the billions.
True Circuits is headquartered at 333 W. El Camino Real, Suite 220, Sunnyvale, California 94087 and can be found on the web at www.truecircuits.com. Product inquiries can be made by calling the company directly at (650) 949-3400 or via e-mail at sales@truecircuits.com.
Press Contact: Kimberly Toan, True Circuits, Inc., (650) 949-3400, Ext. 3404, kim@truecircuits.com.
Acronyms and definitions:
ASIC Application Specific IC IP Intellectual Property
DLL Delay-Locked Loop ONFI Open NAND Flash Interface
DDR Double Data Rate PLL Phase-Locked Loop
FPGA Field Programmable Gate Array SoC System on a Chip
IC Integrated Circuit