Sankalp Semiconductor to present technical paper at CDNLive Bangalore
Bangalore, India - September 5, 2018 - Sankalp Semiconductor a design service company offering comprehensive digital & mixed signal SoC solutions, will be presenting paper at CDNLive India 2018 during 6th & 7th September. The selected paper talks in depth on the “Automated Test Case Creation for Design Rule Deck Validation (DRDV)”. The paper will cover the following key points
- PDK and its validation process
- Rule deck validation flows
- Automation that we have developed for rule deck verification.
When: From 3:00 PM to 3:30 PM on 6th September 2018
Where: Radisson Blu Hotel, Bengaluru, India
Contact: marcom@sankalpsemi.com
About CDNLive
CDNLive India 2018 brings together Cadence® technology users, developers, and industry experts for networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems.
https://www.cadence.com/content/cadence-www/global/en_US/home/cdnlive/india-2018.html
|
Related News
- Sankalp Semiconductor to present technical paper at CDNLive Bangalore
- Sankalp Semiconductor to Exhibit & Present at Design & Reuse IPSoC Santa Clara 2019
- Sankalp Semiconductor Opens Second Design Centre in Bangalore
- Sankalp Semiconductor to Exhibit & Present at Design & Reuse IPSoC China 2018
- Sankalp Semiconductor to Present & Exhibit at Design & Reuse IPSoC Santa Clara 2018
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |