Analog Bits to Demonstrates Low Latency PCIe/CXL Gen 5 on Samsung 8nm at SAFE Forum 2021
Sunnyvale, CA, November 16, 2021 - Analog Bits, the industry’s leading provider of low-power mixed-signal IP (Intellectual Property) solutions will be presenting their paper: "PCIe/CXL SERDES- Gen4/5 Enterprise Class SerDes & Lowest Power Gen3/4 Consumer SERDES in Samsung 28nm to 5nm Processes" at Samsung Advanced Foundry Ecosystem (SAFE) Forum.
"Analog Bits low latency SERDES is a key differentiator for high-end enterprise SSD’s and Re-timer SoC’s that are optimizing for performance and throughput," said Mahesh Tirupattur, Executive Vice President at Analog Bits. “And our close collaboration with Samsung gives us the opportunity to help our mutual customers deliver the best possible latency and performance to the end customers in Gen5 and Gen6 in future. We truly appreciate our years of strategic partnership with Samsung.”
When: November 17-18, 2021
Resources
To learn more about Analog Bits' foundational analog IP, visit www.analogbits.com or email us at info@analogbits.com.
About Analog Bits
Founded in 1995, Analog Bits, Inc. (www.analogbits.com), is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SoCs.
Our products include precision clocking macros, Sensors, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s. With billions of IP cores fabricated in customer silicon, from 0.35- micron to 3nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.
|
Related News
- Alphawave Semi and InnoLight Extend PCIe over Optics Collaboration with Demonstration of 128Gbps Gen 7.0 over Low Latency Linear Pluggable Optics at ECOC 2024
- Samsung and Its Foundry Partners Reveal Solutions for a Strong Design Infrastructure at 3rd SAFE Forum 2021
- Analog Bits to Present Papers, Demo of N5 Working Silicon, and Roadmap on IPs for TSMC N4 and N3 Processes
- Silex Insight extends their AES-GCM Crypto Engine offering by introducing an ultra-low latency version for PCI Express 5.0 and Compute Express Link 2.0
- Analog Bits to demonstrate Low Power SERDES at TSMC's Open Innovation Platform Ecosystem Forum
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |