30mA, Capless High PSRR LDO Regulator for RF and Analog Applications in TSMC 28nm
MIPS selects Imperas Reference Models for RISC-V Processor Verification
Imperas RISC-V golden reference models and Verification IP used for functional RISC-V Processor Verification and Architectural Compatibility Testing
Oxford, United Kingdom, November 29th, 2021 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced with MIPS, Inc., the processor technology company focused on the commercialization of RISC-based processor architectures and IP cores, the continuation and extension to the long-standing relationship with simulation and verification support for RISC-V. Since 2010, MIPS has partnered with Imperas for proprietary simulation technology and reference models for both internal engineering and customer ISS solutions. As the design and verification team transitions to the RISC-V open ISA (Instruction Set Architecture), the Imperas reference models for RISC-V form the essential reference for the processor functional verification tasks.
The latest RISC-V verification ‘step-and-compare’ methodology can be used to verify an RTL processor implementation against the Imperas golden reference model encapsulated within a SystemVerilog environment. This covers asynchronous events and offers a seamless, time-saving transition to debug analysis when an issue is found. More details on test benches with Imperas RISC‑V verification reference models are available at www.imperas.com/riscv.
Since the main role of a central processor is to execute software, software plays a major role in the complete design cycle from the initial project concept to the detailed functional verification, and in the case of processor IP, beyond into the final SoC design and end application development. SoC developers select processor IP based on many factors, however, one of the key deliverables that supports the ease of use is a high-quality ISS to support software development. Since 2010, the MIPS core IP deliverables have included the Imperas based ISS, and as a consequence Imperas technology has helped to support many projects in applications such high-performance wireless communications, networking, automotive and AI applications, with major customers including MediaTek and Intel Mobileye.
“As the MIPS design and verification teams transition to RISC-V, we see a lot of benefits from adopting the open ISA specification,” said Don Smith, Director of Engineering at MIPS, Inc. “As an IP company, we have a significant focus on the quality and verification of our processor IP deliverables. Imperas are the leaders in RISC-V simulation and verification and, with more than a decade of collaboration, they are the obvious DV partner for MIPS and its new RISC-V offerings.”
“RISC-V is at the forefront of a hardware design renaissance in optimized processors,” said Itai Yarom, VP of Sales and Marketing at MIPS, Inc. “But, an ISA only provides the envelope of possibilities. The art and science of processor optimization requires complete feature exploration and verification, which are supported by the reference model simulation and verification technology from Imperas.”
“The Imperas simulation technology has two unique attributes, it models processors with the accuracy, control, and visibility required for functional DV and secondly, it can be integrated into all the main EDA verification environments.” said Simon Davidmann, CEO at Imperas Software Ltd. “Integrating our RISC-V reference models into a SystemVerilog UVM testbench supports the latest techniques for asynchronous events with ‘step-and-compare’, and provides a single environment to efficiently resolve issues. With this expanded partnership, we are thrilled to support the MIPS strategy for RISC-V.”
At CDNLive in Munich, Germany, May 6-8 2019, Intel Mobileye presented a technical paper, “Hybrid Virtual + Emulation SoC Platform for SW-Drivers Validation”, which highlighted the full Linux OS boot in 32 seconds instead of 2-3 hours on the non-hybrid emulation. This was followed by the Imperas presentation discussing hybrid emulation with Imperas reference models and Cadence Palladium for a MIPS-based SoC. These presentations (SVG02, SVG03) are available for download, with free Cadence registration, at this link.
In 2018, the announcement of the MIPS I7200 multi-threaded multicore processor included highlights from MediaTek for 5G compute performance and Imperas for simulators, virtual platforms, and debug and analysis solutions that help accelerate software development for multicore and multi-threaded processor configurations. The full release is available at this link.
Availability
The Imperas RISC-V reference models and processor verification IP are available now; more details are available at www.imperas.com/riscv.
The free riscvOVPsimPlus package, including several Architectural Validation test suites and support for instruction coverage analysis, are now available on OVPworld at www.OVPworld.org/riscvOVPsimPlus.
RISC-V Summit 2021
The RISC-V Summit and DAC are co-located for 2021, running December 6-8 in San Francisco, CA.
Imperas is a Diamond Sponsor for the RISC-V Summit 2021; more details on all the keynotes, talks and to request a demo are available at this link.
About MIPS
MIPS is a leading provider of RISC-based processor architectures and IP cores that drive some of the world’s most popular products. With the streamlined MIPS RISC-based architecture and CPU cores, semiconductor designers can create efficient, scalable and trusted products across a wide range of performance points – from the IoT Edge to high-end networking equipment, and everything in between. Further details are available at www.mips.com.
About Imperas
Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open-source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multicore systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.
For more information about Imperas, please see www.imperas.com.
|
Related News
- OpenHW Ecosystem Implements Imperas RISC-V reference models for Coverage Driven Verification of Open Source CORE-V processor IP cores
- MIPS Selects Imperas for Advanced Verification of High-Performance RISC-V Application-class Processors
- Imperas announce first reference model with UVM encapsulation for RISC-V verification
- Ventana Micro Selects Imperas Solutions for RISC-V Processor Verification
- NSITEXE Qualifies Imperas RISC-V Reference Models for Akaria Processors NS72A, NS72VA, and NS31A
Breaking News
- Panasonic Automotive Systems and Arm Partner to Standardize Software-Defined Vehicles
- Ceva, Inc. Announces Third Quarter 2024 Financial Results
- Logic Fruit Technologies Launches JESD204D Transmitter and Receiver IP - Advancing High-Bandwidth Data Solutions
- Sondrel announces that it is opening up its library of IP for licensing
- Tessolve to Acquire Germany's Dream Chip Technologies
Most Popular
- 珠海创飞芯:基于28 纳米高压工艺制程的OTP IP 实现上架
- Jolt Capital buys and invests in Dolphin Design's carved-out mixed-signal IP activities
- Arteris Announces Financial Results for the Third Quarter 2024 and Fourth Quarter and Full Year 2024 Guidance
- Tessolve to Acquire Germany's Dream Chip Technologies
- M31 Launches USB4 IP for TSMC 5nm Process
E-mail This Article | Printer-Friendly Page |