SkyWater CEO Expands "Technology Foundry" Model
By Alan Patterson, EETimes (November 22, 2022)
SkyWater Technology CEO Thomas Sonderman is building a new type of chip foundry that shifts onerous multi-billion–dollar fab investments to customers who bear most of the cost.
The only 100% U.S.-owned foundry was created in 2017 after private equity investor Oxbow Industries acquired Cypress Foundry Solutions, a subsidiary of now-defunct Cypress Semiconductor, and installed former AMD executive Sonderman at the helm of the new company.
By creating a “technology-foundry model, we went after this sweet spot of the customization/volume gap that required a lot of innovation,” Sonderman told EE Times in an exclusive interview. “It also allowed us to market ourselves as different than just another specialty foundry.”
E-mail This Article | Printer-Friendly Page |
Related News
- PsiQuantum Expands Development Engagement and Plan for Production Ramp of Quantum Computing Technology at SkyWater's Minnesota Fab
- SkyWater Technology Expands Borrowing Capacity by Closing New $100 Million Senior Secured Revolving Credit Facility
- Fabless IC Company Sales "Shine" While IDM IC Sales "Slump" in 2012
- Foundries not dead, just evolving, says Globalfoundries CEO
- Lip-Bu Tan quit Intel board after "differences" with CEO, says Reuters
Breaking News
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- Breaking Ground in Post-Quantum Cryptography Real World Implementation Security Research
- RIKEN adopts Siemens' emulation and High-Level Synthesis platforms for next-generation AI device research
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
Most Popular
- Eighteen New Semiconductor Fabs to Start Construction in 2025, SEMI Reports
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Imagination pulls out of RISC-V CPUs
- Chip Interfaces Successfully Completes Interlaken IP Interoperability Test with Cadence 112G Long-Reach PHY
- RISC-V in AI and HPC Part 2: Per Aspera Ad Astra?