Jan. 12, 2023, Jan. 12, 2023 –
By Dan Kochpatcharin, TSMC
EETimes (January 11, 2023)
As design teams continue to develop new generations of transformative products, the demand for compute remains relentless. Modern workloads have brought packaging technologies to the forefront for innovation and pushed the boundaries for silicon product design in terms of product performance, function and cost. Not too long ago, packaging technologies were thought of as inconvenient back-end processes. But times have changed, and rising advancements in artificial intelligence, big data, cloud computing and autonomous vehicles have pushed the computing envelope unlike ever before (along with the need for packaging technologies).
This computing evolution has resulted in the shrinking of chips and the emergence of multi-die architectures, creating a promising landscape for 3D silicon stacking and advanced packaging innovation for optimized system performance. 3D ICs offer a practical way to promise a whole new level of power, performance, area and functionality.
However, the right choice of packaging depends on many factors, and designers need help navigating the best path through the myriad options and approaches available. To speed up the adoption and production of future 3D ICs, the semiconductor industry needs a streamlined, collaborative ecosystem that can provide best-in-class optimization at the system level.