Search IP on TSMC

DesignWare DDR5/4 PHY IP for TSMC N7

Low-Power IEEE 802.11a/b/g/n 2.4/5 GHz SISO Wi-Fi TSMC40

HBM2E PHY on TSMC 7FF

• JEDEC standard supported: JESD235A & JESD235B
• DFI 4.0 interface compatible
• 8 channels with 1024 DQs per HBM Gen2 Stack

Voltage Monitor with Digital Output TSMC N5 (Multi-domain supply monitoring)

• On-chip Core & I/O supply monitoring
• Low supply voltage alarms
• IR Drop monitoring for core logic

112G XSR Multi-protocol SerDes PHY

• Supports up to 8 duplex lanes and data rates from 25 to 112 Gbps
• Ultra-low power configurable architecture for D2D and D2OE interfaces

2-ch 16-bit stereo Audio ADC

2-ch 24-bit 192KSPS Audio DAC

10/100 Ethernet PHY

• TSMC 22nm ULP
• support EEE

7nm High-Bandwidth Interconnect (HBI+) PHY for Die-to-Die Interconnects

Wi-Fi WPA3 MAC

• Legacy security system
• WPA/WPA2 security system (IEEE 802.11i)
• Protection of Management Frames (IEEE 802.11w)

Power On Reset

Core Voltage Regulator

• Input voltage range 3.0V – 3.3V.
• Output voltage 1.2V or 1.8V ±4%.
• Output short circuit protection.