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eFPGA Tile with power management for TSMC 40ULP & 40LP

• Metal Stack: 7 layer metal
• Nominal Supply Voltages (Vj): 1.1 V
• Junction Temperature (°C): −40 to 125

Power Line Communications, PLC, Transceiver, N-PLC, G3-PLC, Prime, IEEE, Sunspec

6-bit, 1 GSPS High Performance AFE in 28nm CMOS

14-bit, 1200 MSPS Ultra Low Power AFE in 28nm CMOS

AC-DC converter 220/110VAC to 5V-1.8VDC

• 180nm TSMC BCD process
• 85 to 265V AC input
• Configurable 1.8V to 5.0V DC Output

9 track Near Threshold Voltage standard cell library at TSMC 55 nm

7 track High Density standard cell library at TSMC 40 nm

7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V / 1.1 V)

6 track Ultra High Density standard cell library at TSMC 180 nm

24-Bit Continuous Time Sigma Delta Audio ADC

• TSMC 40nm ULP Process
• 1.1V & 1.8V Supplies
• Continuous-Time Sigma-Delta ADC

350MHz Single-ended to Differential ADC Buffer

• TSMC 40nm LP (Low Power Process)
• Analog Options: Deep N-Well
• 1.1V Core & 2.5V I/O Supplies

Fully Digital Glitch Free PLL TSMC 16FFC 16 nm - 300-3000 MHz