Search IP on TSMC

DesignWare® PHY IP for PCIe 5.0 on Samsung 8LPP

112Gbps XSR SerDes IP for TSMC 7nm FinFET

• Interoperability
• Maximize beach front bandwidth
• Layout flexibility

Analog-PLL For Spread Spectrum Clock

• TSMC 28nm HPM/HPC
• Including Loop-filter
• VCO operating range : 900MHz - 1800 MHz

USB4 PHY IP in TSMC 7FF for 40 Gbps Performance

• Supports USB4, USB 3.2, DisplayPort with HDCP 2.3 security, PCI Express, and Thunderbolt 3 connectivity protocols through USB Type-C connectors and cables

Rambus 32G Medium Reach Multi-Protocol SerDes PHY

MIPI D-PHY CSI-2 RX+ 1.5Gbps for Automotive Applications

• Supports MIPI Alliance Specification for D-PHY Version 2.5
• Consists of 1 Clock lane and 2 Data lanes
• Embedded, high performance, and highly programmable PLL

Customizable Video Input Controller with color space conversion

• Configurable Input Formats
• Configurable Output Formats
• Configurable Codeword Correction

PHY IP for PCIe 5.0 on TSMC N6

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
• Lane margining at the receiver

Analog PLL on TSMC 28nm HPM/HPC

• Including Loop-filter
• VCO operating range : 2500MHz - 5000 MHz
• Output frequency range : 1250MHz - 2500 MHz

CryoCMOS IP to Unlock Quantum Computing

• Specially Engineered CryoCMOS IP
• Characterised down to 4°K
• Minimal Power Dissipation

DC/DC - Audio Grade Buck Regulator - TSMC 0.18um

LPDDR5/LPDDR4 combo PHY on 14nm, 12nm

• JESD209-5A(LPDDR5), JESD209-4C(LPDDR4), JESD209-4-1(LPDDR4X) compliant
• Operating speed up to 6400Mbps in LPDDR5, 4266Mbps in LPDDR4X
• Multiple DFICLK : CK :WCK ratios