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End-to-end design and verification for PCIe 6.0
By Nick Flaherty, eeNews Europe (July 10, 2023)
PCI Express (PCIe) 6.0 is gaining traction in AI, HPC, and data centres, operating at 64GT/s, twice as fast as the previous generation. Network servers, SSDs, switches, and AI accelerators are all early adopters of PCIe 6.0, and network interface cards (NIC) and CPU host chips are on the horizon.
PCIe 6.0 is a transformative serial bus interface technology, a kind of sea change in interconnect based on several technological shifts in this version of the specification, say Gary Ruggles, Senior Product Manager and Madhumita Sanyal, Sr. Staff Technical Product Manager at Synopsys.
PAM-4 pulse amplitude signaling at four voltage levels produces three eyes, a shift from traditional non-return to zero (NRZ) signaling. Precoding and forward error correction (FEC) will reduce errors for analog and digital, respectively. This delivers 64GT/s bandwidth with low latency.
Flow control unit (FLIT) packet delivery is a new architecture for packet delivery (required due to the FEC) not only supports the increased bandwidth but also enables your system to support it.
The L0p low-power state allows some lanes to go into a sleep mode as bandwidth requirements decrease in the system. This gives you the ability to optimize your power consumption while never shutting down the link.
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