SureCore announces low power cryogenic memory technology that could help dramatically cut data centre power usage

Sheffield, England, 4 June 2024 – One of the big challenges with data centres is amount of power that they consume. This is being further exacerbated by the increasing use of AI in the form of Large Language Models. Studies have shown that cooling power hungry processing chips to the temperature of liquid nitrogen at around 77K results in a seven-fold power usage reduction but just under half of this advantage is lost in cooling costs. However, with power prices spiralling, a potential four-fold reduction is certainly getting a lot of industry attention.

SureCore has developed technology that has enabled it to design memory solutions for quantum computing applications that can operate down to 4K. This technology is equally applicable to 77K operation. As both server chips and AI processors integrate large amounts of SRAM migrating to sureCore’s low power cryogenic memory could help data centres run cooler by reducing SRAM power dissipation with the added benefit of significantly reducing the cooling load.

Paul Wells, sureCore’s CEO explained, “As part of an InnovateUK funded project, we have worked closely with our partner Semiwise who have developed cryogenic transistor SPICE models. These have enabled us to port and tune our low power memory technology to work at temperatures down to 4K. The goal was not only to develop memory for cryogenic operation, but also to exploit our power saving techniques so as to minimise the thermal load in the cryostat. For a datacentre operating at 77K, similar challenges apply and, by saving up to 50% of the memory power, a significant cut in thermal dissipation is possible with knock-on effects for the cooling power budget.”

Professor Asen Asenov, CEO of SemiWise, added, “The key to successfully enabling the AI revolution is the availability of access to accurate cryogenic transistor SPICE models. This will allow IP developers to create suites of IP so that SoC developers can create next generation AI server chips. SemiWise has developed unique technology to engineer PDK-strength cryogenic SPICE models based on a limited suite of cryogenic measurements supplemented by TCAD simulations.”

sureCore has exploited its state-of-the-art, ultra-low power memory design skills to create embedded Static Random Access Memory (SRAM), an essential building block for any digital sub-system, that is capable of operating from 77K (-196°C) down to the near absolute zero temperatures needed by Quantum Computers (QCs). In addition, both standard cell and IO cell libraries have been re-characterised for operation at cryogenic temperatures thereby enabling an industry standard RTL to GDSII physical design flow to be readily adopted. SureCore’s CryoMem range of IP is part of an Innovate UK project that sureCore is leading with test chips soon to be evaluated at cryo temperatures.

Wells concluded, “We are very excited that a new application area has opened up for our ultra-low power memory technologies. Data centres have a heat problem and we can potentially provide a solution.”

sureCore^™ -- When low power is paramount^™

sureCore, the ultra-low power, embedded memory specialist, is the low-power innovator who empowers the IC design community to meet aggressive power budgets through a portfolio of ultra-low power memory design services and standard IP products. sureCore’s low-power engineering methodologies and design flows meet the most exacting memory requirements with a comprehensive product and design services portfolio that create clear market differentiation for customers. The company’s low-power product line encompasses a range of close to near-threshold, silicon proven, process-independent SRAM IP.

www.sure-core.com

SemiWise Limited

SemiWise develops innovative low-power CMOS transistor-level IP that improves performance and variability, and drastically reduces power consumption. SemiWise also offers simulation services and consulting to the semiconductor industry including fables, IEDM and foundry players. The CEO of Semiwise, Professor Asenov was the founder of Gold Standard Simulations (GSS), a 2010 startup from the University of Glasgow which developed the first TCAD based Design- Technology Co Optimisation (DTCO) tool chain. After the acquisition of GSS by Synopsys in 2016 the TCAD-to-Spice technology originally developed by GSS is now part of the Synopsys TCAD offering in the so called TCAD-to-Spice flow and continues to be developed by the Synopsys R&D division in Glasgow.

www.semiwise.uk

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