Addressing AI While Keeping the MIPSiness In MIPS

By Sally Ward-Foxton, EETimes (July 5, 2024)

SANTA CLARA, Calif. — MIPS, now targeting AI applications for its application-specific data movement cores, is evolving with a careful eye on its strengths. “MIPS had a choice to make, because most of our RISC-V competitors are also publicly, or not publicly, pivoting hard towards AI,” MIPS CEO Sameer Wasson told EE Times. “The choice we made was to look at the problems others are not solving well and try to match them with what we can do better.”

RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications 64-bit RISC-V Application Processor Core RISC-V-based AI IP development for enhanced training and inference

For MIPS, this means data movement—something both deeply embedded in MIPS’ history and expertise, and absolutely critical to performant AI chips and systems.

“The problem we want to solve is to build the best data processing engine,” Wasson said. “It’s a mission which may not have the buzz to it [versus AI IP], relatively speaking, but I’m very comfortable with it, frankly, because it allows us to fly under the radar.”

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