Arasan Announces immediate availability of its SPMI IP (System Power Management Interface)
Arasan Chip Systems, a leading provider of semiconductor IP for mobile and automobile SoCs, today announced the immediate availability of its MIPI SPMI IP
Dec 9, 2024, San Jose, CA -- Arasan expands its MIPI IP portfolio with the announcement of the immediate availability of its SPMI IP (System Power Management Interface) compliant to MIPI SPMI Specificationv2.0.
The System Power Management Interface (SPMI) IP is a standardized protocol developed by the MIPI Alliance to facilitate efficient power management in complex system-on-chip (SoC) designs. It is particularly crucial in applications where power consumption needs to be minimized without compromising performance, such as in mobile devices, wearables, and other battery-powered electronics.
Block Diagram of Arasan SPMI Host/Device IP
Features of SPMI IP:
- Low-Latency Communication
- Scalability
- Dynamic Voltage and Frequency Scaling (DVFS)
- Multi-Master Support
- Power Efficiency
Arasan’s offers the industry’s broadest MIPI IP portfolio including IP for CSI-2, DSI, DSI-2, UNIPRO, Slimbus, Soundwire, I3C, D-PHY, C-PHY, M-PHY and now SPMI.
Availability
The Arasan SPMI IP is available immediately for ASIC and FPGA applications. Arasan is a member of both Xilinx, Intel and Microsemi FPGA IP Partner Programs.
About Arasan:
Arasan Chip Systems is a leading provider of IP for mobile storage and mobile connectivity interfaces, with over a billion chips shipped with our IP. Our high-quality, silicon-proven Total IP Solutions encompass digital IP, Analog Mixed Signal PHY IP, Verification IP, HDK, and Software. With a strong focus on mobile SoCs, we have been at the forefront of the “Mobile” evolution since the mid-90s, supporting various mobile devices, including smartphones, automobiles, drones, and IoT devices, with our standards-based IP.
|
Arasan Chip Systems Hot IP
Related News
- Arasan announces the immediate availability of its ultra-low power MIPI D-PHY IP for the GlobalFoundries 12nm FinFET process node
- Arasan announces the immediate availability of its Ultra Low Power MIPI D-PHY IP Compliant to D-PHY Specification v1.20 for TSMC 22nm SoC Designs
- Arasan Announces immediate availability of its I3C Host / Device Dual Role Controller IP
- Arasan Announces immediate availability of its SUREBOOT™ Total xSPI PHY IP
- Arasan announces the immediate availability of its 2nd Generation MIPI D-PHY for GlobalFoundries 22nm SoC Designs
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |