English
SmartDV to Demonstrate TileLink Verification IP for RISC-V Based Systems, Smart ViPDebug Protocol Debugger at DVCon India
Will Highlight Broad Portfolio of VIP for Simulation, Emulation, Formal, FPGA Prototyping and Design IP
SAN JOSE, CALIF –– September 11, 2019 ––
WHO: SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP) supporting simulation, emulation, field programmable gate array (FPGA) prototyping, formal models and post-silicon validation platforms, Design IP and rapid customized VIP and Design IP development
WHAT: Will demonstrate TileLink VIP used to verify the TileLink chip-scale interconnect standard, an open-source, high-performance and scalable cache-coherent fabric for RISC-V based system on chip (SoC) designs at DVCon India. Another demonstration will showcase Smart ViPDebug™, a protocol debugger that reduces debug time by rapidly identifying violations and reducing the time needed to find the cause of violations through its linked waveform and transaction database views.
WHEN: Wednesday and Thursday, September 25 and 26. Attendees can schedule demonstrations through: demo@smart-dv.com
WHERE: Radisson Blu Bengaluru in Bangalore, India
About SmartDV
SmartDV™ Technologies is the Proven and Trusted choice for Verification and Design IP with the best customer service from more than 250 experienced ASIC and SoC design and verification engineers. Its high-quality standard or custom protocol Verification and Design IP are compatible with all verification languages, platforms and methodologies supporting all simulation, emulation, FPGA prototyping and formal verification tools used in a coverage-driven chip design verification flow. The result is Proven and Trusted Verification and Design IP used in hundreds of networking, storage, automotive, bus, MIPI and display chip projects throughout the global electronics industry. SmartDV is headquartered in Bangalore, India, with U.S. headquarters in San Jose, Calif. Visit SmartDV to learn more.
|
||||||
SmartDV Technologies Hot IP
SmartDV Technologies Hot Verification IP
Related News
- SmartDV Heads to DVCon Europe to Showcase VIP Support for Verilator and TileLink, Demonstrate Smart ViPDebug Protocol Debugger
- NSITEXE Selects SmartDV TileLink Verification IP for RISC-V Based Applications
- SmartDV's TileLink, Verilator VIP on Full Display at RISC-V Summit
- SmartDV Supports RISC-V Movement with TileLink Verification IP for RISC-V Based Systems
- Truechip Adds New Customer Shipments of Verification IPs For RISC-V Family Including TileLink
Breaking News
- Optimized SAR ADCs, Sigma-Delta ADCs, DACs, and Audio CODECs for IoT, MCU, SoC, and Consumer Applications
- Enabled on makeChip and powered by Racyics, the SpiNNaker2 chip forms the core of the newly launched SpiNNcould supercomputer!
- Semidynamics Announces Cervell™ All-in-One RISC-V NPU Delivering Scalable AI Compute for Edge and Datacenter Applications
- Weebit Nano and DB HiTek to demonstrate chips integrating Weebit ReRAM at PCIM 2025
- Silvaco Expands Product Offerings in Photonics and Wafer-Scale Plasma Modeling for AI Applications with Acquisition of Tech-X Corporation
Most Popular
- Keysight EDA and Intel Foundry Collaborate on EMIB-T Silicon Bridge Technology for Next-Generation AI and Data Center Solutions
- IC'Alps joins Intel Foundry Accelerator program as Value Chain Alliance (VCA) and Design Services Alliance (DSA) partner
- Intel Foundry Gathers Customers and Partners, Outlines Priorities
- Weebit Nano and DB HiTek to demonstrate chips integrating Weebit ReRAM at PCIM 2025
- Semidynamics Announces Cervell™ All-in-One RISC-V NPU Delivering Scalable AI Compute for Edge and Datacenter Applications
|
E-mail This Article | 
|
|
Printer-Friendly Page |