Rambus Advances HBM2E Performance to 4.0 Gbps for AI/ML Training Applications
SAN JOSE, Calif. – Sept. 9, 2020 – Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced it has achieved a record 4 Gbps performance with the Rambus HBM2E memory interface solution consisting of a fully-integrated PHY and controller. Paired with the industry’s fastest HBM2E DRAM from SK hynix operating at 3.6 Gbps, the solution can deliver 460 GB/s of bandwidth from a single HBM2E device. This performance meets the terabyte-scale bandwidth needs of accelerators targeting the most demanding AI/ML training and high-performance computing (HPC) applications.
“With this achievement by Rambus, designers of AI and HPC systems can now implement systems using the world’s fastest HBM2E DRAM running at 3.6 Gbps from SK hynix,” said Uksong Kang, vice president of product planning at SK hynix. “In July, we announced full-scale mass-production of HBM2E for state-of-the-art computing applications demanding the highest bandwidth available.”
Related |
HBM2/2E Memory Controller Core |
The fully-integrated, production-ready Rambus HBM2E memory subsystem runs at 4 Gbps without PHY voltage overdrive. Rambus teamed with SK hynix and Alchip to implement the HBM2E 2.5D system to validate in silicon the Rambus HBM2E PHY and Memory Controller IP using TSMC’s N7 process and CoWoS® (Chip-on-Wafer-on-Substrate) advanced packaging technologies. Co-designing with the engineering team from Rambus, Alchip led the interposer and package substrate design.
“This advancement of Rambus and its partners, using TSMC’s advanced process and packaging technologies, is another important achievement of our ongoing collaboration with Rambus,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “We look forward to a continued partnership with Rambus to enable the highest performance in AI/ML and HPC applications.”
“Alchip brought a demonstrated track record of success in 7nm and 2.5D package design to this initiative,” said Johnny Shen, CEO of Alchip Technologies. “We’re extremely proud of our contributions to Rambus’ breakthrough achievement.”
Rambus has 30 years of high-speed memory design applied to the most demanding computing applications. Its renowned signal integrity expertise was key to achieving an HBM2E memory interface capable of 4 Gbps operation. This raises a new benchmark for meeting the insatiable bandwidth requirements of AI/ML training.
“With silicon operation up to 4 Gbps, designers can future-proof their HBM2E implementations and can be confident of ample margin for 3.6 Gbps designs,” said Matthew Jones, senior director and general manager of IP cores at Rambus. “As part of every customer engagement, Rambus provides reference designs for the 2.5D package and interposer to ensure first-time right implementations for mission-critical AI/ML designs.”
Figure 1: Rambus HBM2E Interface 4 Gbps Transmit Eye
Benefits of the Rambus HBM2E Memory Interface (PHY and Controller):
- Achieves the industry’s highest speed of 4 Gbps per pin, delivering a system bandwidth of 460 GB from a single 3.6 Gbps HBM2E DRAM 3D device.
- Fully-integrated and verified HBM2E PHY and Controller reduces ASIC design complexity and speeds time to market
- Includes 2.5D package and interposer reference design as part of IP license
- Provides access to Rambus system and SI/PI experts helping ASIC designers to ensure maximum signal and power integrity for devices and systems
- Features LabStation™ development environment that enables quick system bring-up, characterization and debug
- Supports high-performance applications including state-of-the-art AI/ML training and high-performance computing (HPC) systems
For more information on the Rambus Interface IP, including our PHYs and Controllers, please visit rambus.com/interface-ip.
|
Related News
- Rambus Advances AI/ML Performance with 8.4 Gbps HBM3-Ready Memory Subsystem
- Rambus Boosts AI Performance with 9.6 Gbps HBM3 Memory Controller IP
- PLDA Announces XpressRICH4-AXI PCIe 4.0 IP, Providing a High Performance and Reliable AXI Bridge for SoC designs
- Rambus Advances Data Center Server Performance with Industry-First Gen4 DDR5 RCD
- SiFive Announces Differentiated Solutions for Generative AI and ML Applications Leading RISC-V into a New Era of High-Performance Innovation
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024
E-mail This Article | Printer-Friendly Page |