ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
Movellus Announces Industry-First Integrated Droop Response System for SoCs
Sunnyvale, California -- June 13th, 2023 – Movellus, today announced an industry-first integrated droop response system. This innovative solution is designed to simultaneously address the challenges of voltage droop and enable fine-grained DVFS capability, which in combination can significantly reduce the power consumption of complex integrated circuits while increasing operational reliability. In addition to detecting and responding to voltage droops, the solution incorporates extensive monitoring and observability features that will provide valuable insight to modern silicon health and lifecycle management systems.
The AWM2 system adaptation time is amongst the fastest in the industry – similar in performance to full custom solutions but offered as off-the-shelf synthesizable IP. This can result in power saving of more than 10%, making it ideal for complex, power-sensitive SoCs.
“The true power of our digital IP platform is demonstrated in our new droop response system,” said Mo Faisal, CEO of Movellus, “We added autonomous, programmable behavior to our adaptive clocking solution, inserted observability functionality for silicon health and analytics, and developed a cohesive droop response solution that can be delivered as off the shelf IP.”
The integrated droop response system combines droop detection and compensation into a complete integrated system, reducing effort while still gaining maximum benefit. The system’s observability also provides design engineers greater visibility into SoC performance, enabling them to make informed decisions and apply optimal silicon life cycle management strategies.
“In today’s fiercely competitive IC markets, improvements in power efficiency and performance can be a difference-maker,” said Dave Fick, co-founder and CEO at Mythic. “Movellus’ Droop Response System squeezes improvements from the voltage and frequency guardbands that we typically take for granted. Finding these hidden savings and making them easy to deploy is why Movellus is such a great partner to work with.”
“In the age of many high-performance processors on an SOC, the old rules of thumb about activity factors no longer apply. Even if you have TDP headroom, regulators and on-chip power delivery may not be able to keep up with 1000+ processors all going from idle to full-blast computation,” said Darren Jones, vice president of VLSI engineering at Esperanto Technologies. “Hardware designers need tools and solutions to solve transient supply droop. The traditional solution is to over-design, operate at a higher voltage, and even lower performance to protect against catastrophic circuit failures. With better tools to identify and better solutions to mitigate transient supply droop, we can operate with higher performance and lower power.”
Key features of the integrated droop response system IP include:
- Extremely fast time to adapt (detect + respond) for droop with fine-grained clock speed selection
- Extremely fast response time for DVFS control
- Industry first observable droop response system for silicon health and analytics management
- Multi-threshold droop detection
- Support for remote and local droop detection
- APB and JTAG interfaces for silicon health and analytics management during bringup, at production test, and during in field operation
Availability
The Aeonic Generate™ AWM2 is now sampling to select customers. More information on the AWM2 system can be found on the product page or by visiting us at DAC in San Francisco, California (Booth #2417) July 9-13th 2023.
About
Movellus provides critical technology that is integrated into an array of applications ranging from edge AI devices to performance-centric cloud datacenter compute and networking offerings. The team is headquartered in Sunnyvale with R&D centers in Michigan and Toronto. Visit us at: www.movellus.com
|
Related News
- Movellus Debuts Industry-First On-Die Power Delivery Network Analyzer
- Cadence Advances AI in the Cloud with Industry-First DDR5 12.8Gbps MRDIMM Gen2 Memory IP System Solution
- SLS Launches Industry-First USB 20Gbps Device IP Core
- Droop response system IP made available for SoC designs
- Synopsys Announces Industry-First Unified Functional Safety Verification Solution to Accelerate Time-to-Certification for IPs and SoCs
Breaking News
- Agile Analog appoints CEO to drive growth
- Numem Appoints Former Intel Executives to Leadership Team
- Optimized SAR ADCs, Sigma-Delta ADCs, DACs, and Audio CODECs for IoT, MCU, SoC, and Consumer Applications
- Enabled on makeChip and powered by Racyics, the SpiNNaker2 chip forms the core of the newly launched SpiNNcould supercomputer!
- Semidynamics Announces Cervell™ All-in-One RISC-V NPU Delivering Scalable AI Compute for Edge and Datacenter Applications
Most Popular
- Keysight EDA and Intel Foundry Collaborate on EMIB-T Silicon Bridge Technology for Next-Generation AI and Data Center Solutions
- IC'Alps joins Intel Foundry Accelerator program as Value Chain Alliance (VCA) and Design Services Alliance (DSA) partner
- Intel Foundry Gathers Customers and Partners, Outlines Priorities
- Weebit Nano and DB HiTek to demonstrate chips integrating Weebit ReRAM at PCIM 2025
- Semidynamics Announces Cervell™ All-in-One RISC-V NPU Delivering Scalable AI Compute for Edge and Datacenter Applications
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |