Design & Reuse
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arrow Embedded Memories (1005)
arrow I/O Library (992)
arrow Standard cell (745)
2786 IP
2401
0.118
Dual Port SRAM Compiler IP, UMC 0.18um eFlash/G2 process
UMC 0.18um eFlash GII Logic process high density Dual Port SRAM compiler....
2402
0.118
Dual Port SRAM Compiler IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous high density Dual Port (2RW) SRAM memory compiler....
2403
0.118
Dual Port SRAM Compiler IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous high density Dual Port (2RW) SRAM memory compiler....
2404
0.118
Dual Port SRAM Compiler IP, UMC 0.18um MS process
UMC 0.18um MM/RF process synchronous high density Dual Port SRAM memory compiler....
2405
0.118
Dual Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP/ Low-K Dual Port SRAM compiler....
2406
0.118
Dual Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP Logic process, Dual Port SRAM compiler with LVT....
2407
0.118
Dual Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP Logic process, Dual Port SRAM compiler with R1....
2408
0.118
Dual Port SRAM Compiler IP, UMC 55nm eHV process
UMC 55nm eHV process, Dual Port SRAM compiler....
2409
0.118
Dual Port SRAM Compiler IP, UMC 55nm LP process
UMC 55nm LP Logic process Synchronous Dual Port SRAM memory compiler....
2410
0.118
Dual Port SRAM Compiler IP, UMC 55nm LP process
UMC 55nm LP/ Low-K process with row Redundancy Dual Port SRAM compiler....
2411
0.118
Dual Port SRAM Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process Low Power synchronous high density Dual Port SRAM memory compiler....
2412
0.118
Dual Port SRAM Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process synchronous Dual Port RAM memory compiler....
2413
0.118
Dual Port SRAM Compiler IP, UMC 65nm LL process
UMC 65nm low leakage RVT Logic Low_K process synchronous high density Dual Port SRAM memory compiler with bist testing interface....
2414
0.118
Dual Port SRAM Compiler IP, UMC 65nm LL process
UMC 65nm low leakage RVT Logic Low_K process synchronous high density Dual Port SRAM memory compiler....
2415
0.118
Dual Port SRAM Compiler IP, UMC 65nm SP process
UMC 65nm 1.0V SP Low-K Logic process synchronous high density Dual Port SRAM compiler (with row redundancy option)....
2416
0.118
Dual Port SRAM Compiler IP, UMC 90nm LL process
UMC 90nm LL/RVT Low-K Logic process Synchronouslow AC power Dual Port SRAM....
2417
0.118
Dual Port SRAM Compiler IP, UMC 90nm LL process
UMC 90nm LL/RVT Synchronous high density Dual Port SRAM memory compiler....
2418
0.118
Dual Port SRAM Compiler IP, UMC 90nm SP process
UMC 90nm SP/RVT/ Low-K process synchronous Dual Port SRAM compiler....
2419
0.118
Fujitsu 90mm LL-HS process MPCA core cell library [Minimum progeamming layer = M3/4/5 (MUST thin metal layers)]
Fujitsu 90mm LL-HS process MPCA core cell library [Minimum progeamming layer = M3/4/5 (MUST thin metal layers)]...
2420
0.118
Fujitsu 90nm LL-UHS process MPCA M345 core cell library
Fujitsu 90nm LL-UHS process MPCA M345 core cell library...
2421
0.118
Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process Multi-Voltage metal programmable IO Cell Library....
2422
0.118
Multi-Voltage IO IP, BOAC (Bonding Over Active Circuit), UMC 0.15um SP process
UMC 0.15um SP process standard Multi-Voltage IO....
2423
0.118
Multi-Voltage IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um LL process
UMC 0.18um LL Logic process standard Multi-Voltage IO....
2424
0.118
LVDS Receiver IP, 8MHz - 135MHz, UMC 0.13um SP/FSG process
2.5V LVDS Receiver 8~135MHz, UMC 90nm SP process....
2425
0.118
LVDS Receiver IP, 20MHz - 135MHz , UMC 0.18um G2 process
DLL-based LVDS RX, VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation frequency, UMC 0.13um HS FSG Logic process....
2426
0.118
LVDS Receiver IP, 20MHz - 135MHz , UMC 0.18um HS/FSG process
20M~135MHz DLL-based LVDS RX, UMC 0.13um HS/FSG process....
2427
0.118
LVDS Receiver IP, 500Mbps, UMC 55nm LP process
LVDS RX IO PAD 500Mbps, UMC 55nm LP/RVT Low-K Logic process....
2428
0.118
LVDS Receiver IP, 700Mbps, UMC 0.13um SP/FSG process
Low Power LVDS Receiver 700Mbps, UMC 90nm SP/RVT Low-K Logic process....
2429
0.118
LVDS Receiver IP, Clock: 16 MHz - 120 MHz, 6:42 data lane expansion for throughput up to 5040 Mbps, UMC 40nm LP process
LVDS RX, UMC 40nm LP/RVT Low-K Logic process....
2430
0.118
LVDS Receiver IP, UMC 90nm SP process
DLL-based LVDS RX, UMC 55nm SP/RVT Low-K Logic process....
2431
0.118
LVDS Rx IO IP, 500Mbps, UMC 90nm LL process
Low Power LVDS Receiver IO 500Mbps, UMC 55nm SP/RVT Low-K Logic process....
2432
0.118
LVDS Rx IO IP, UMC 0.18um G2 process
0.13um LVDS RX IO PAD, UMC 0.13um HS/HVT-FSG process....
2433
0.118
LVDS Rx IO IP, UMC 0.18um Logic process
LVDS RX IO, UMC 90nm SP/RVT Low-K Logic process....
2434
0.118
LVDS Rx IO IP, UMC 90nm SP process
0.18UM RX (PAD), UMC 0.18um GII Logic process....
2435
0.118
LVDS RX IO PAD 300 Mbps with combo GPIO , UMC 55nm eflash/RVT LowK Logic Process
LVDS RX IO PAD 300 Mbps with combo GPIO , UMC 55nm eflash/RVT LowK Logic Process...
2436
0.118
LVDS RX IO PAD 500 Mbps ,UMC 40nm LP/RVT LowK Logic Process
LVDS RX IO PAD 500 Mbps ,UMC 40nm LP/RVT LowK Logic Process...
2437
0.118
LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, Bump pad.
LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, Bump pad....
2438
0.118
LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip
LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip...
2439
0.118
LVDS Transmitter 700Mbps; UMC 28nm HPC Process
LVDS Transmitter 700Mbps; UMC 28nm HPC Process...
2440
0.118
LVDS Transmitter IP, 8MHz - 100MHz, 4 channels, UMC 0.18um G2 process
3.3V 4 channel LVDS Transmitter 8~100MHz, UMC 90nm SP/RVT Low-K process....
2441
0.118
LVDS Transmitter IP, 8MHz - 135MHz, 4 channels, UMC 0.13um SP/FSG process
2.5V 4 channel LVDS Transmitter 8~135MHz, UMC 90nm SP/RVT Low-K process....
2442
0.118
LVDS Transmitter IP, 1200Mbps, UMC 55nm SP process
1.8V Sub-LVDS Transmitter 1200Mbps, UMC 40nm LP/RVT Logic process....
2443
0.118
LVDS Transmitter IP, 16MHz - 178MHz, UMC 55nm SP process
2.5V LVDS Transmitter 16~178MHz, UMC 55nm SP/RVT Low-K Logic process....
2444
0.118
LVDS Transmitter IP, 700Mbps, UMC 0.13um SP/FSG process
3.3V LVDS Transmitter 700Mbps, UMC 90nm SP/RVT low-L process....
2445
0.118
LVDS Transmitter IP, 700Mbps, UMC 55nm SP process
2.5V LVDS Transmitter 700Mbps, UMC 40nm LP Low-K Logic process....
2446
0.118
LVDS Transmitter IP, 700Mbps, UMC 90nm SP process
3.3V LVDS Transmitter 700Mbps, UMC 55nm SP/RVT Low-K process....
2447
0.118
LVDS Transmitter IP, 700Mbps, UMC 90nm SP process
2.5V LVDS Transmitter 700Mbps, UMC 55nm SP Low-K Logic process....
2448
0.118
LVDS Transmitter IP, 85MHz, UMC 55nm SP process
1.8V/3.3V 85MHz 35:5 LVDS Transmitter, UMC 0.18um GII Logic process....
2449
0.118
LVDS Transmitter IP, 8MHz - 135MHz , UMC 0.13um HS/FSG process
8M~135MHz DLL-based LVDS TX, UMC 0.13um HS/FSG process....
2450
0.118
LVDS Transmitter IP, 8MHz - 135MHz, UMC 90nm SP process
2.5V LVDS Transmitter 8~135MHz, UMC 90nm SP process....