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5497 IP
2801
0.118
RC Oscillator IP, Output: 64KHz, UMC 0.13um HS/FSG process
Internal-R, output frequency 64KHz, Input 1.08V-1.32V, Oscillator, UMC 0.13um Logic HS FSG process....
2802
0.118
RC Oscillator IP, Output: 70MHz, UMC 0.11um HS/AE process
Internal-R, trimmable fixed frequency 70MHz. Input 1.08V-1.32V, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process....
2803
0.118
RC Oscillator IP, Output: 70MHz, UMC 0.11um HS/AE process
Internal-RC, trimmable fixed frequency 70MHz & 82.5MHz. Power Supply: 1.14V-1.26V, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process....
2804
0.118
RC Oscillator IP, Output: 70MHz, UMC 0.11um HS/FSG process
Internal-RC, trimmable fixed frequency 70MHz. Input 1.08V-1.32V VBG=0.8V, UMC 0.11um HS/FSG Logic process....
2805
0.118
RC Oscillator IP, Output: 70MHz, UMC 0.11um HS/FSG process
Internal-RC, trimmable fixed frequency 70MHz Power Supply: 1.14V-1.26V, UMC 0.11um HS/FSG Logic process....
2806
0.118
RC Oscillator IP, Output: 70MHz, UMC 0.13um HS/FSG process
Internal-RC, trimmable fixed frequency 70MHz. Input 1.08V-1.32V VBG=0.8V, UMC 0.13um HS/FSG Logic process....
2807
0.118
RC Oscillator IP, Output: 80MHz, UMC 0.18um G2 process
Internal-RC, trimmable frequency 80MHz. Input 1.62V-1.98V, VBG=0.615V, UMC 0.18um GII Logic process....
2808
0.118
RC Oscillator IP, RC-Oscillator, Output: 32KHz, UMC 0.13um HS/AE process
Internal-R, trimmable fixed frequency 70MHz. Input 1.08V-1.32V VBG=0.8V, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process....
2809
0.118
DC-DC IP, Input: 0.95V - 1.5V, Output: 3V/100mA, UMC 0.11um HS/AE process
0.95V~1.5V to 3.0V DC-DC converter with 100mA driving capability, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process....
2810
0.118
DC-DC IP, Input: 2.5V - 4.2V, Output: 3.3V/50uA, HJTC 0.18um eFlash/G2 process
Input 2.5V~4.2V, Output=3.3V, Loading 50uA charge pump PWM Regulator, HJTC 0.18um eFlash 1.8V/3.3V/5V process....
2811
0.118
DC-DC IP, Input: 2.5V / 3.3V, Output: 1.05V/250mA, UMC 0.11um HS/AE process
2.5V/3.3V to 1.05V high efficiency converter with 250mA driving capability, compensation built-in, PWM regulator, UMC 0.11um HS/AE (AL Advanced Enhanc...
2812
0.118
DC-DC IP, Input: 3.3V, Output: +/- 12.5V / +6V, UMC 0.35um Logic process
Three pulse width modulation, boosting voltage from 3.3V to +/-12.5V, and +6V, Ivcca=450uA @ Idrive=0....
2813
0.118
DC-DC IP, Input: 3.3V, Output: 3.3V/300mA, UMC 0.153um MS process
5.0V to 3.3V high efficiency converter with 300mA driving capability PWM Regulator, UMC 0.153um 1.8V/3.3V Logic/Mixed-Mode process....
2814
0.118
DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 0.11um HS/AE process
3V~3.6V to 5V DC-DC converter with 100mA driving capability, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process....
2815
0.118
DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 40nm LP process
Boosting voltage from 3.3V to 5V, 100mA driving capability, Pulse Width Modulator, UMC 40nm Logic LP/RVT Low-K process....
2816
0.118
DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 65nm SP process
Boosting voltage from 3.3V to 5V, 100mA driving capability, Ivcca=200uA @ Idrive=0, Pulse Width Modulator, UMC 65nm SP/HVT Logic Low-K process....
2817
0.118
DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 90nm SP process
Boosting voltage from 3.3V to 5V, 100mA driving capability, Ivcca=200uA @ Idrive=0mA, Pulse Width Modulator, UMC 90nm SP/RVT Low-K process....
2818
0.118
DC-DC IP, Input: 3.3V, Output: 5V/50mA, HJTC 0.18um eFlash/G2 process
PWM charge pump with internal soft start function. The input voltage is 3.3V. The output voltage is 5V with 50mA driving, HJ 0.18um eFlash process....
2819
0.118
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.153um MS process
Pulse Width Modulation, boosting voltage from 3.3V to 5V/50mA driving capability, Ivcca=140uA@Idrive=0, UMC 0.153um Logic/Mixed-Mode process....
2820
0.118
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.18um G2 process
Pulse width modulation, boosting voltage from 3.3V to 5V, 50mA driving capability, Ivcca=140uA @ Idrive=0....
2821
0.118
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.25um Logic process
Pulse width modulation, boosting voltage from 3.3V to 5V, 50mA driving capability, Ivcca=150uA @ Idrive=0....
2822
0.118
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 65nm LL process
DC-DC Power converter, Input:3.0V~3.6V, output:5V, 50mA loading, UMC 65nm LL/RVT Low_K process....
2823
0.118
DC-DC IP, Input: 5V, Output: 3.3V/300mA, UMC 0.11um HS/AE process
5.0V to 3.3V high efficiency converter with 300mA driving capability PWM Regulator, UMC 0.11um 1.2V/3.3V HS/AE (AL Advanced Enhancement) Logic process...
2824
0.118
DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.2V/50mA, UMC 0.13um HS/FSG process
3.3V to 1.2V high efficiency converter with 50mA driving capability, PWM Regulator, UMC 0.13um HS/FSG Logic process....
2825
0.118
DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.8V/150mA, with soft-start, UMC 0.13um LL/FSG process
3.3V to 1.8V high efficiency converter with 150mA driving capability, PWM Regulator, UMC 0.13um LL Logic/FSG process....
2826
0.118
DC-DC IP, Step-down PWM Regulator, Input: 3.0V - 3.6V, Output: 1.8V/200mA, with soft-start, UMC 0.13um HS/FSG process
3.3V to 1.8V high efficiency converter with 200mA driving capability PWM Regulator, UMC 0.13um HS/FSG Logic process....
2827
0.118
DC-DC IP, Step-up PWM Regulator, Input: 3.0V - 3.6V, Output: 5V/100mA, with soft-start, UMC 0.13um HS/FSG process
PWM controller with soft start function for DC to DC boost converter, UMC 0.13um HS/FSG Logic process....
2828
0.118
DDR DLL (All Digital) IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...
2829
0.118
DDR DLL IP, 100MHz - 200MHz, Output: 13.5% - 36.6% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhanceme...
2830
0.118
DDR DLL IP, 100MHz - 400MHz, Output: 25% Delay, UMC 0.13um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.13um HS/FSG process....
2831
0.118
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/AE process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic ...
2832
0.118
DDR DLL IP, 200MHz - 400MHz, Output: 25% Delay, UMC 0.11um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/RVT Logic process....
2833
0.118
DDR DLL IP, Input: 100MHz - 150MHz, Output: 100MHz - 150MHz, UMC 0.18um G2 process
Input 100M-150MHz, output 100M-150MHz, DDR DLL, UMC 0.18um GII Logic process....
2834
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.13um HS/FSG process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.13um HS/FSG Logic process....
2835
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.15um SP process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.15um SP Logic process....
2836
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.162um LL process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.162um Logic process....
2837
0.118
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz -200MHz, UMC 0.18um G2 process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.18um GII Logic process....
2838
0.118
DDR DLL IP, Input: 100MHz - 400MHz, Output: 100MHz - 400MHz, UMC 65nm SP process
Input 100-400MHz, output 100-400MHz, DDR2 DLL, UMC 65nm SP/RVT Low-K Logic process....
2839
0.118
DDR DLL IP, Input: 192MHz - 400MHz, Output: 96MHz - 200MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG process DLL-based cell that generates fouRchannel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage....
2840
0.118
DDR DLL IP, Input: 200MHz - 333MHz, Output: 200MHz - 333MHz, UMC 90nm SP process
Input 200-333MHz, output 200-333MHz, DDR2 DLL, UMC 90nm SP/RVT Low-K Logic process....
2841
0.118
DDR DLL IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, UMC 55nm SP process
Input 200-400MHz, output 200-400MHz, DDR2 DLL, UMC 55nm SP Low-K Logic process....
2842
0.118
DDR DLL IP, Input: 333MHz - 667MHz, Output: 333MHz - 667MHz, UMC 90nm SP process
Input 333M-667MHz, output 333M-667MHz, DDR2/3 Multi-phase DLL, UMC 90nm SP/RVT Low-K Logic process....
2843
0.118
DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
It is a UMC 0.13um HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller usage....
2844
0.118
DDR DLL IP, Input: 66MHz - 133MHz, Output: 66MHz - 133MHz, UMC 0.13um HS/FSG process
Input 66M-133MHz, output 66M-133MHz, DDR DLL, UMC 0.13um HS/FSG Logic process....
2845
0.118
DDR DLL IP, Input: 66MHz - 200MHz, Output: 66MHz - 200MHz, UMC 90nm SP process
Input 66M-200MHz, output 66M-200MHz, DDR DLL, UMC 90nm SP/RVT Low-K Logic process....
2846
0.118
DDR DLL IP, Input: 80MHz - 320MHz, Output: 6.25%-50% Delay, UMC 55nm SP process
Input 80-320MHz, output 6.25%~50% delay, 80-320MHz, DDR2 DLL, UMC 55nm SP/RVT Low-K Logic process....
2847
0.118
Self-contained ring oscillator, frequency 32KHz. VCC11A=1.08V~1.32V; UMC 55nm LP/RVT Low-K Logic process
Self-contained ring oscillator, frequency 32KHz. VCC11A=1.08V~1.32V; UMC 55nm LP/RVT Low-K Logic process...
2848
0.118
OFDM AFE using UMC 55nm eFlash Process
OFDM AFE using UMC 55nm eFlash Process...
2849
0.118
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process...
2850
0.118
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process...