Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Chip to Chip (9)
arrow Die-to-die (93)
arrow Intra SoC Connectivity (20)
23 IP
1
16.0
Die-2-die interfaces for chiplets - GPIOs for 2.5D and 3D integration
Analog I/O and on-chip Electrostatic Discharge (ESD) protection. Proven on many foundries: TSMC, UMC, GF, TowerSemi, Samsung Foundry, ... Proven in ...
2
9.0308
UCIe 2.0 PHY for Standard Package (8nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, and 24GT/s with a 64...
3
9.0
IPT UCIE 2.0 CONTROLLER
High-Performance UCIe Controller IP for AI, Data Center & Consumer Applications The InPsytech UCIe 2.0 (Universal Chiplet Interconnect Express) Contr...
4
8.5077
UCIe Controller for Standard Package
UCIe v2.0 controller implements the D2D Adapter defined in the UCIe 2.0 specification, as well as AXI4-to-Flit protocol conversion. The D2D Adapter su...
5
5.0556
600Mbps Low Power D2D Interface in TSMC 16nm
Custom die-to-die interface in 16nm process technology. The I/O cell is bi-directional and has two modes of operation: standard rail-to-rail swing or ...
6
5.0556
<4Gbps Low Power D2D Interface in TSMC 12/16nm
Custom die-to-die interface in 12/16nm process technology. The I/O cells are defined as TX only, and RX only and have two modes of operation, standard...
7
5.0556
<4Gbps Low Power D2D Interface in TSMC 28nm
Custom die-to-die high-speed interface in 28nm process technology. The I/O cells are defined as TX only, and RX only, and have two modes of operation,...
8
0.0
D2D (Die-to-Die) Interconnect IP in WhiteBox, Unlimited Usage
This die-to-die interconnect IP Core is defined as an AIB IP Core, which is optimized for 32-bit AXI data transfer, enabling Master-to-Slave AXI trans...
9
0.0
D2D PHY, ADVANCED PACKAGE, 3nm
The InPsytech (IPT) D2D PHY IP is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed...
10
0.0
D2D PHY, ADVANCED PACKAGE, 7nm/6nm
The InPsytech (IPT) D2D PHY is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed da...
11
0.0
D2D PHY, STANDARD PACKAGE, 7nm/6nm
The InPsytech (IPT) D2D PHY is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed da...
12
0.0
UCIe Protocol Layer: AXI-S
The AXI-S Protocol Layer for UCIe is a protocol adapter layer between a Streaming AXI Bus and the FDI interface of the UCIe D2D Adapter. It allows for...
13
0.0
UCIE-A PHY, 5nm/4nm
The InPsytech (IPT) UCIe-A PHY is a mass-production proven, state-of-the-art physical layer interface designed to provide exceptional performance and ...
14
0.0
UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
15
0.0
Chiplet Solution
Based on the traditional advantages of SerDes and DDR IP, KNiulink Semiconductor has launched a solution that meets the UCIe standard based on local r...
16
0.0
Die-to-Die PHY
Eliyan uses its NuLink technology to develop die-to-die PHY IP products to support multiple standards (including UCIe and BoW) and multiple packaging ...
17
0.0
Blumind Chiplet
Contact us to learn more about Neural Signal Processor known-good-die for system in package integration....
18
0.0
Universal Chiplet Interconnect Express PHY IP GlobalFoundries® 22FDX®
The Racyics UCIe PHY is an energy-efficient chiplet interconnect IP solution for consumer and automotive applications. Implemented in 22FDX technology...
19
0.0
IPT 64GT/S UCIE-A PHY
The UCIe-A_HS 64Gbps Die-to-Die (D2D) PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects between...
20
0.0
IPT 64GT/S UCIE-S PHY,
The high-speed UCIe-S 64G is a cutting-edge standard package die-to-die (D2D) and chiplet-to-chiplet (C2C) interface IP solution designed to enable ul...
21
0.0
IPT D2D CONTROLLER
The InPsytech high-speed D2D Controller IP, optimized for power and latency enables die-to-die or chiplet-to-chiplet connectivity in applications like...
22
0.0
IPT LOW POWER UCIE-A PHY
The Ultra-low power UCIe-A Die-to-Die PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-low-power system demand with up...
23
0.0
IPT UCIE-S PHY
The IPT UCIe-S is a cutting-edge standard package die-to-die (D2D) and chiplet-to-chiplet (C2C) interface IP solution designed to enable high-speed an...