Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Chip to Chip (30)
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50 IP
1
75.0
64G UCIe Standard PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
2
60.0
TSMC CLN6FF/7FF Die-to-Die Interface PHY
IGAD2DX01A is a high speed die-to-die interface PHY which transmits data through INFO RDL channels. IGAD2DX01A contains 32 Tx lanes and 32 Rx lanes pe...
3
25.0
32G UCIe Advanced PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
4
20.0
D2D(UCIe 1.0)
The Die-to-Die interface is a functional block that provides a data interface between two chip dies in the same package. MSquare's M2LINK D2D Solution...
5
20.0
D2D(UCIe 1.1)
The Die-to-Die interface is a functional block that provides a data interface between two chip dies within the same package. MSquare's D2D solution, c...
6
16.0
Die-2-die interfaces for chiplets - GPIOs for 2.5D and 3D integration
Analog I/O and on-chip Electrostatic Discharge (ESD) protection. Proven on many foundries: TSMC, UMC, GF, TowerSemi, Samsung Foundry, ... Proven in ...
7
15.0
32G UCIe Standard PHY for Samsung
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
8
15.0
32G UCIe Standard PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
9
14.0
UCIe 2.0 Subsystem for Standard Package (5nm) SF5A (PHY + Adapter + Protocol Mapper)
Controller Overview: UCIe v2.0 controller implements the D2D Adapter defined in the UCIe 2.0 specification, as well as AXI4-to-Flit protocol conversi...
10
14.0
UCIe 2.0 Subsystem for Standard Package (8nm) 8LPU (PHY + Adapter + Protocol Mapper)
Controller Overview: UCIe v2.0 controller implements the D2D Adapter defined in the UCIe 2.0 specification, as well as AXI4-to-Flit protocol conversi...
11
14.0
UCIe 2.0 Subsystem for Standard/Advanced Package (4nm) SF4X (PHY + Adapter + Protocol Mapper)
Controller Overview: UCIe v2.0 controller implements the D2D Adapter defined in the UCIe 2.0 specification, as well as AXI4-to-Flit protocol conversi...
12
14.0
UCIe 3.0 Subsystem for Standard Package (2nm) SF2P (PHY + Adapter + Protocol Mapper)
The UCI Express Specification Revision 3.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, 24GT/s, 32GT/s, 48GT...
13
12.5
45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
The IKAIKA45GRX is the first generation of UCIe-Class receiver macro on GF 45SPCLO technology node supporting from 1 to 32Gbps with 70mV sensitivity. ...
14
12.5
45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
The IKAIKA45GTX is the first generation of UCIe-Class transmitter macro on GF 45SPCLO technology node supporting from 1 to 32Gbps with 800mVpp single ...
15
10.0
MAXVY Universal Chiplet Interconnect Express (UCIe) Verification IP
MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of you...
16
9.0
IPT UCIE 2.0 CONTROLLER
High-Performance UCIe Controller IP for AI, Data Center & Consumer Applications The InPsytech UCIe 2.0 (Universal Chiplet Interconnect Express) Contr...
17
5.0
UF16 D2D: <4Gbps low-power die-to-die interface, TSMC 16nm
A silicon-proven, low-power die-to-die interface in TSMC 16nm (FFC/FFC+) for flip-chip / multi-die assembly. Separate TX-only and RX-only cells run in...
18
5.0
VX16: 600Mbps low-power D2D interface, TSMC 16nm FFC/FFC+
A custom, low-power die-to-die interface in TSMC 16nm FFC/FFC+. The bidirectional I/O cell (VX_HSIO) runs in two modes: standard full rail-to-rail swi...
19
1.0
UD28: <4gnps low-power die-to-die interface, TSMC 28nm
A silicon-proven, low-power die-to-die interface in TSMC 28nm (HPM/HPC/HPC+) for flip-chip / multi-die assembly. Separate TX-only and RX-only cells ru...
20
0.0
40G Ultralink D2D PHY for GLOBALFOUNDRIES
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity. The Cadence® UltraLin...
21
0.0
40G Ultralink D2D PHY for Samsung
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity. The Cadence® UltraLin...
22
0.0
40G Ultralink D2D PHY for TSMC
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity. The Cadence® UltraLin...
23
0.0
D2D (Die-to-Die) Interconnect IP in WhiteBox, Unlimited Usage
This die-to-die interconnect IP Core is defined as an AIB IP Core, which is optimized for 32-bit AXI data transfer, enabling Master-to-Slave AXI trans...
24
0.0
D2D PHY, ADVANCED PACKAGE, 3nm
The InPsytech (IPT) D2D PHY IP is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed...
25
0.0
D2D PHY, ADVANCED PACKAGE, 7nm/6nm
The InPsytech (IPT) D2D PHY is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed da...
26
0.0
D2D PHY, STANDARD PACKAGE, 7nm/6nm
The InPsytech (IPT) D2D PHY is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed da...
27
0.0
16G UCIe Advanced PHY for Intel
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
28
0.0
16G UCIe Advanced PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
29
0.0
16G UCIe Advanced PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
30
0.0
16G UCIe Standard PHY for Samsung
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
31
0.0
16G UCIe Standard PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
32
0.0
16G UCIe Standard PHY for TSMC Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
33
0.0
UALink PHY + Controller
INNOSILICON unveils its UALink PHY and Controller IP, engineered specifically to meet the AI era’s demanding high-performance SoC requirements. The so...
34
0.0
UCIe 2.0 Subsystem for Advanced Package (4nm) SF4X (PHY + Adapter + Protocol Mapper)
Controller Overview: UCIe v2.0 controller implements the D2D Adapter defined in the UCIe 2.0 specification, as well as AXI4-to-Flit protocol conversi...
35
0.0
UCIe 2.0 Subsystem for Advanced Package (8nm) 8LPU (PHY + Adapter + Protocol Mapper)
Controller Overview: UCIe v2.0 controller implements the D2D Adapter defined in the UCIe 2.0 specification, as well as AXI4-to-Flit protocol conversi...
36
0.0
UCIe Controller for Standard Package
UCIe v2.0 controller implements the D2D Adapter defined in the UCIe 2.0 specification, as well as AXI4-to-Flit protocol conversion. The D2D Adapter su...
37
0.0
UCIe Protocol Layer: AXI-S
The AXI-S Protocol Layer for UCIe is a protocol adapter layer between a Streaming AXI Bus and the FDI interface of the UCIe D2D Adapter. It allows for...
38
0.0
UCIE-A PHY, 5nm/4nm
The InPsytech (IPT) UCIe-A PHY is a mass-production proven, state-of-the-art physical layer interface designed to provide exceptional performance and ...
39
0.0
UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
40
0.0
Chiplet Solution
Based on the traditional advantages of SerDes and DDR IP, KNiulink Semiconductor has launched a solution that meets the UCIe standard based on local r...
41
0.0
Die-to-Die PHY
Eliyan uses its NuLink technology to develop die-to-die PHY IP products to support multiple standards (including UCIe and BoW) and multiple packaging ...
42
0.0
Blumind Chiplet
Contact us to learn more about Neural Signal Processor known-good-die for system in package integration....
43
0.0
Universal Chiplet Interconnect Express PHY IP GlobalFoundries® 22FDX®
The Racyics UCIe PHY is an energy-efficient chiplet interconnect IP solution for consumer and automotive applications. Implemented in 22FDX technology...
44
0.0
IPT 64GT/S UCIE-A PHY
The UCIe-A_HS 64Gbps Die-to-Die (D2D) PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects between...
45
0.0
IPT 64GT/S UCIE-S PHY,
The high-speed UCIe-S 64G is a cutting-edge standard package die-to-die (D2D) and chiplet-to-chiplet (C2C) interface IP solution designed to enable ul...
46
0.0
IPT D2D CONTROLLER
The InPsytech high-speed D2D Controller IP, optimized for power and latency enables die-to-die or chiplet-to-chiplet connectivity in applications like...
47
0.0
IPT LOW POWER UCIE-A PHY
The Ultra-low power UCIe-A Die-to-Die PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-low-power system demand with up...
48
0.0
IPT UCIE-S PHY
The IPT UCIe-S is a cutting-edge standard package die-to-die (D2D) and chiplet-to-chiplet (C2C) interface IP solution designed to enable high-speed an...
49
0.0
TSMC CLN6FF/7FF Die-to-Die Interface PHY
This IGAD2DX01A test report shows the functional and characterization test result of GUC Die-to-Die Interface PHY IP for 8 Gbps operation. For IP deta...
50
0.0
Synopsys UCIe Controller IP for Automotive
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...