Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Chip to Chip (24)
arrow Die-to-die (112)
arrow Intra SoC Connectivity (20)
24 IP
1
10.0
Chip-to-Chip IO Buffer - TSMC CLN4P
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
2
10.0
Chip-to-Chip IO Buffer - TSMC CLN5
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
3
10.0
Chip-to-Chip IO Buffer - TSMC CLN5A
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
4
10.0
Chip-to-Chip IO Buffer - TSMC CLN6FF
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
5
10.0
Chip-to-Chip IO Buffer - TSMC CLN7FF
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
6
5.0
SPI Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
7
5.0
SPI Slave Controller (SPI2APB, SPI2AXI, SPI2AHB Bus)
The Digital Blocks DB-SPI-S-AMBA-BRIDGE is a Serial Port Interface (SPI) Controller Verilog IP Core supporting SPI Slave Interface to APB Master Bus. ...
8
2.0
I3C Master / Slave Controller - MIPI Basic v1.0
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – BASIC ...
9
0.0
I3C Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...
10
0.0
I3C Master Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...
11
0.0
I3C Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-S-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improve...
12
0.0
UMI™ for Die-to-Memory (D2M) PHY IP
Unlike fixed unidirectional die-to-die solutions, NuLink technology is able to deliver low-power and high-performance D2M solutions....
13
0.0
Innovative Ultra-High-Speed Chiplet Solution
Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chip...
14
0.0
XPHY Low power Chip to Chip SerDes IP, Silicon Proven in ST 28FDSOI
These IPs are targeted at applications requiring high speed, high bandwidth, low-power consumption, and low-latency interfaces....
15
0.0
SPI Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
16
0.0
SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
17
0.0
SPI Master Controller w/FIFO (AHB & AHB-Lite Bus)
The Digital Blocks DB-SPI-M is a Serial Port Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and...
18
0.0
SPI Master Controller w/FIFO (APB Bus)
The Digital Blocks DB-SPI-M is a Serial Port Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and...
19
0.0
SPI MRAM/PSRAM Memory Controller
The DB-SPI-M-PSRAM-AXI4 is a SPI Master Memory Controller IP core purpose-built for the Avalanche Technology AS30xG208 / ASAS308G208 family of space-g...
20
0.0
eSPI Controller RTL SystemVerilog IP
Digital Blocks' DB-eSPI-Controller-AMBA is a fully synthesizable SystemVerilog IP Core conforming to the eSPI 1.6 Specification for Controller (Master...
21
0.0
eSPI Controller/Target RTL SystemVerilog IP
Digital Blocks' DB-eSPI-Controller-Target-AMBA is a highly versatile, fully synthesizable SystemVerilog IP Core conforming to the eSPI 1.6 Specificati...
22
0.0
eSPI Target RTL SystemVerilog IP
Digital Blocks' DB-eSPI-Target-AMBA is a fully synthesizable SystemVerilog IP Core conforming to the eSPI 1.6 Specification for Target (Slave) applica...
23
0.0
Nutcracker XSR Connectivity Chiplet
Core and analog logic may not always deploy at the same time in the same process. Maturing high performance analog typically takes longer in moving to...
24
0.0
AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
The Digital Blocks DB-SPI-FLASH-CTRL is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad SPI Flash...