Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Chip to Chip (12)
arrow Die-to-die (109)
arrow Intra SoC Connectivity (20)
12 IP
1
10.0
Chip-to-Chip IO Buffer - TSMC CLN4P
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
2
10.0
Chip-to-Chip IO Buffer - TSMC CLN5
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
3
10.0
Chip-to-Chip IO Buffer - TSMC CLN5A
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
4
10.0
Chip-to-Chip IO Buffer - TSMC CLN6FF
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
5
10.0
Chip-to-Chip IO Buffer - TSMC CLN7FF
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
6
0.0
UMI™ for Die-to-Memory (D2M) PHY IP
Unlike fixed unidirectional die-to-die solutions, NuLink technology is able to deliver low-power and high-performance D2M solutions....
7
0.0
Innovative Ultra-High-Speed Chiplet Solution
Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chip...
8
0.0
XPHY Low power Chip to Chip SerDes IP, Silicon Proven in ST 28FDSOI
These IPs are targeted at applications requiring high speed, high bandwidth, low-power consumption, and low-latency interfaces....
9
0.0
eSPI Controller RTL SystemVerilog IP
Digital Blocks' DB-eSPI-Controller-AMBA is a fully synthesizable SystemVerilog IP Core conforming to the eSPI 1.6 Specification for Controller (Master...
10
0.0
eSPI Controller/Target RTL SystemVerilog IP
Digital Blocks' DB-eSPI-Controller-Target-AMBA is a highly versatile, fully synthesizable SystemVerilog IP Core conforming to the eSPI 1.6 Specificati...
11
0.0
eSPI Target RTL SystemVerilog IP
Digital Blocks' DB-eSPI-Target-AMBA is a fully synthesizable SystemVerilog IP Core conforming to the eSPI 1.6 Specification for Target (Slave) applica...
12
0.0
Nutcracker XSR Connectivity Chiplet
Core and analog logic may not always deploy at the same time in the same process. Maturing high performance analog typically takes longer in moving to...