Design & Reuse
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23 IP
1
16.0
Die-2-die interfaces for chiplets
Analog I/OS and power line ESD solutions All voltage domains (0.75V to 5V) Additional voltage (e.g. 12V in 28nm proven)...
2
14.0
40G Ultralink D2D PHY for GF12LP+
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
3
14.0
40G Ultralink D2D PHY for Samsung 7LPP
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
4
14.0
Universal Chiplet Interconnect Express (UCIe 1.0) Controller
Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller i...
5
11.0
Die-to-Die (D2D) Interconnect
Lightweight die-to-die interconnect solution optimized for highest performance with the lowest power and area overhead...
6
10.0
UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
Unleash the power of the new UCIe based RF Chiplet transceiver. With NEXT Semiconductor's silicon proven 8-bit, 48-Gsps Transceiver, this product ...
7
3.0
600Mbps Low Power D2D Interface in 16nm
Custom die-to-die interface in 16nm process technology. The I/O cell is bi-directional and has two modes of operation: standard rail-to-rail swing or ...
8
3.0
<4Gbps Low Power D2D Interface
Custom die-to-die high-speed interface in 28nm process technology. The I/O cells are defined as TX only, and RX only, and have two modes of operation,...
9
0.0
2-16Gbps Die-to-Die (D2D) Multi-Protocol IO Supporting BOW, OHBI and UCIe
The AresCORE 16G Die-to-Die (D2D) IP implements a wide-parallel and clock forwarded PHY interface for multichannel interconnections up to 16Gbps. The ...
10
0.0
D2D PHY (Die-to-Die Interface)
Die-to-Die (D2D) PHY IP is based on HBM electrical specification and will also be compatible with upcoming interface standards. It is used specificall...
11
0.0
D2D Controller IP (Die-to-Die Interface)
OpenFive s Die-to-Die (D2D) Controller IP is targeted for heterogenous chiplet solutions in wired communications, AI and HPC applications. With recent...
12
0.0
33G Die-to-Die SerDes PHY (12nm 16nm)
The AnalogX AXDieIO IP utilizes the silicon-proven AXLinkIO transceiver architecture for die-to-die, in package, type of channel links....
13
0.0
25-112Gbps Extra Short-Reach (XSR) Multi-Standard SerDes (MSS)
The Alphawave DieCORE delivers the world s highest density, lowest power die-to-die connectivity solution for MCMs based on OIF XSR/USR serial standar...
14
0.0
UCIe 2.0 Controller
The InPsytech UCIe 2.0 (Universal Chiplet Interconnect Express) Controller is a high-performance designe to facilitate efficient communication between...
15
0.0
UCIe PHY & D2D Adapter
Neuron IP’s UCIe PHY & D2D Adapter IP portfolio includes 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S) cores as per the latest UCIe v1.1 specifica...
16
0.0
Die-to-Die PHY
Eliyan uses its NuLink technology to develop die-to-die PHY IP products to support multiple standards (including UCIe and BoW) and multiple packaging ...
17
0.0
BlueLynx Executable Generator Technology
BlueLynx&trade; technology revolutionizes the game in silicon design and engineering. Using proprietary technology, Blue Cheetah eliminates inefficien...
18
0.0
KNiulink Chiplet Solution
Based on the traditional advantages of SerDes and DDR IP, KNiulink Semiconductor has launched a solution that meets the UCIe standard based on local r...
19
0.0
IPT UCIE-A PHY, Advanced Package
The InPsytech (IPT) UCIe-A PHY is a state-of-the-art physical layer interface, offering industry-leading power efficiency and proven in mass productio...
20
0.0
IPT UCIE-A PHY, TSMC N5/N4P
The InPsytech (IPT) UCIe-A PHY is a mass-production proven, state-of-the-art physical layer interface designed to provide exceptional performance and ...
21
0.0
TSMC CLN6FF/7FF Die-to-Die Interface PHY
IGAD2DX01A is a high speed die-to-die interface PHY which transmits data through INFO RDL channels. IGAD2DX01A contains 32 Tx lanes and 32 Rx lanes pe...
22
0.0
Multi-Die interLink (GLink 2.3) IP
GUC multi-die interLink (GLink) IP provides world’s best class solution for high-bandwidth, low-power, low-latency multi-channel interconnection in a ...
23
0.0
Bunch of Wires [BoW] PHY IP
Blue Cheetah&#39;s Bunch of Wires [BoW] PHY IP design incorporates the maximum benefit of the Open Compute Project&#39;s (OCP) inter-chiplet PHY spec...