Design & Reuse
arrow Chip to Chip (9)
arrow Die-to-die (92)
arrow Intra SoC Connectivity (21)
92 IP
1
100.0
UCIe PHY & D2D Adapter
Neuron IP’s UCIe PHY & D2D Adapter IP portfolio includes 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S) cores as per the latest UCIe v1.1 specifica...
2
100.0
UCIe-A PHY for Advanced Package (x64) in TSMC (N7, N6, N5, N3)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
3
100.0
UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
4
100.0
UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
5
100.0
Universal Chiplet Interconnect Express (UCIe) Controller
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...
6
70.0
40G UCIe PHY IP on Samsung SF4X
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...
7
60.0
TSMC CLN6FF/7FF Die-to-Die Interface PHY
IGAD2DX01A is a high speed die-to-die interface PHY which transmits data through INFO RDL channels. IGAD2DX01A contains 32 Tx lanes and 32 Rx lanes pe...
8
60.0
Multi-Die interLink (GLink 2.3) IP
GUC multi-die interLink (GLink) IP provides world’s best class solution for high-bandwidth, low-power, low-latency multi-channel interconnection in a ...
9
50.0
40G UCIe PHY for high-density advanced packages
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...
10
50.0
40G UCIe PHY for organic substrate standard packages
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...
11
30.0
UCIe Die-to-Die Chiplet Controller
Introducing OPENEDGES’ Universal Chiplet Interconnect Express (UCIe) Controller IP, OUC, designed to transform the semiconductor landscape with innova...
12
30.0
Universal Chiplet Interconnect Express (UCIe) Controller
Integrating multiple chiplets within a single package has become crucial for high-performance computing. CoMira’s UCIe (Universal Chiplet Interconnect...
13
16.0
Die-2-die interfaces for chiplets - GPIOs for 2.5D and 3D integration
Analog I/O and on-chip Electrostatic Discharge (ESD) protection. Proven on many foundries: TSMC, UMC, GF, TowerSemi, Samsung Foundry, ... Proven in ...
14
14.0
40G Ultralink D2D PHY for GF12LP+
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
15
14.0
40G Ultralink D2D PHY for GF12LP+
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
16
14.0
40G Ultralink D2D PHY for Samsung 7LPP
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
17
14.0
40G Ultralink D2D PHY for Samsung 7LPP
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
18
14.0
UltraLink Controller
Ultralink controller for high performance die-to-die interconnect on streaming, CXS, and AXI protocols The Cadence Ultralink Controller enables a pro...
19
14.0
Universal Chiplet Interconnect Express (UCIe 1.0) Controller
Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller i...
20
14.0
Universal Chiplet Interconnect Express (UCIe 1.0) Controller
Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller i...
21
11.0
Die-to-Die (D2D) Interconnect
Lightweight die-to-die interconnect solution optimized for highest performance with the lowest power and area overhead...
22
11.0
Die-to-Die (D2D) Interconnect
Lightweight die-to-die interconnect solution optimized for highest performance with the lowest power and area overhead...
23
10.0
UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
Unleash the power of the new UCIe based RF Chiplet transceiver. With NEXT Semiconductor's silicon proven 8-bit, 48-Gsps Transceiver, this product ...
24
10.0
UCIe D2D Adapter
The D2D Adapter for UCIe is a scalable adapter layer between one or more protocol components and the UCIe PHY, which ensures efficient data transfer a...
25
10.0
Die-to-Die Controller IP
The Synopsys Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accele...
26
10.0
Die-to-Die, 112G Ultra-Extra Short Reach PHY in GF (12nm)
The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...
27
10.0
Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5)
The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...
28
9.0
IPT UCIE 2.0 CONTROLLER
High-Performance UCIe Controller IP for AI, Data Center & Consumer Applications The InPsytech UCIe 2.0 (Universal Chiplet Interconnect Express) Contr...
29
8.0
TSMC CLN5FF Glink 2.0 Die-to-Die PHY
IGAD2DY01A is a high speed die-to-die interface PHY which transmits data through TSMC advanced packaging solutions：Integrated Fan-Out (InFO) with RDL ...
30
5.0556
600Mbps Low Power D2D Interface in TSMC 16nm
Custom die-to-die interface in 16nm process technology. The I/O cell is bi-directional and has two modes of operation: standard rail-to-rail swing or ...
31
5.0556
<4Gbps Low Power D2D Interface in TSMC 12/16nm
Custom die-to-die interface in 12/16nm process technology. The I/O cells are defined as TX only, and RX only and have two modes of operation, standard...
32
5.0556
<4Gbps Low Power D2D Interface in TSMC 28nm
Custom die-to-die high-speed interface in 28nm process technology. The I/O cells are defined as TX only, and RX only, and have two modes of operation,...
33
4.0
UCIe 2.0 PHY for Advanced Package (4nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, 24GT/s and 32GT/s wi...
34
4.0
UCIe 2.0 PHY for Advanced Package (8nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, and 24GT/s with a 64...
35
4.0
UCIe 2.0 PHY for Standard Package (4nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, and 16GT/s with a 16-lane co...
36
4.0
UCIe 2.0 PHY for Standard Package (5nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, and 16GT/s with a 16-lane co...
37
4.0
UCIe 2.0 PHY for Standard Package (8nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, and 24GT/s with a 64...
38
0.0
40G Ultralink D2D PHY for TSMC N3P
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
39
0.0
40G Ultralink D2D PHY for TSMC N5P
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
40
0.0
40G Ultralink D2D PHY for TSMC N6, N7
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
41
0.0
D2D (Die-to-Die) Interconnect IP in WhiteBox, Unlimited Usage
This die-to-die interconnect IP Core is defined as an AIB IP Core, which is optimized for 32-bit AXI data transfer, enabling Master-to-Slave AXI trans...
42
0.0
D2D PHY, ADVANCED PACKAGE, 3nm
The InPsytech (IPT) D2D PHY IP is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed...
43
0.0
D2D PHY, ADVANCED PACKAGE, 5nm/4nm
The InPsytech (IPT) D2D PHY is a mass-production proven, state-of-the-art physical layer interface designed to provide exceptional performance and eff...
44
0.0
D2D PHY, ADVANCED PACKAGE, 7nm/6nm
The InPsytech (IPT) D2D PHY is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed da...
45
0.0
D2D PHY, STANDARD PACKAGE, 7nm/6nm
The InPsytech (IPT) D2D PHY is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed da...
46
0.0
32G UCIe Standard PHY for TSMC N3P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
47
0.0
16G UCIe Advanced PHY for TSMC N3P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
48
0.0
16G UCIe Advanced PHY for TSMC N4P/N5P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
49
0.0
16G UCIe Standard PHY for Samsung SF5A
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
50
0.0
16G UCIe Standard PHY for TSMC N3A Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...