Design & Reuse
Catalog of SIP Cores
System on Chip design resources
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arrow Die-to-die (112)
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112 IP
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40G Ultralink D2D PHY for TSMC N6, N7
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
52
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D2D (Die-to-Die) Interconnect IP in WhiteBox, Unlimited Usage
This die-to-die interconnect IP Core is defined as an AIB IP Core, which is optimized for 32-bit AXI data transfer, enabling Master-to-Slave AXI trans...
53
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D2D PHY, ADVANCED PACKAGE, 3nm
The InPsytech (IPT) D2D PHY IP is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed...
54
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D2D PHY, ADVANCED PACKAGE, 5nm/4nm
The InPsytech (IPT) D2D PHY is a mass-production proven, state-of-the-art physical layer interface designed to provide exceptional performance and eff...
55
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D2D PHY, ADVANCED PACKAGE, 7nm/6nm
The InPsytech (IPT) D2D PHY is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed da...
56
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D2D PHY, STANDARD PACKAGE, 7nm/6nm
The InPsytech (IPT) D2D PHY is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed da...
57
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32G UCIe Standard PHY for TSMC N3P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
58
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16G UCIe Advanced PHY for Intel
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
59
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16G UCIe Advanced PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
60
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16G UCIe Advanced PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
61
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16G UCIe Advanced PHY for TSMC N3P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
62
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16G UCIe Advanced PHY for TSMC N4P/N5P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
63
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16G UCIe Standard PHY for Samsung
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
64
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16G UCIe Standard PHY for Samsung SF5A
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
65
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16G UCIe Standard PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
66
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16G UCIe Standard PHY for TSMC Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
67
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16G UCIe Standard PHY for TSMC N3A Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
68
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16G UCIe Standard PHY for TSMC N4P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
69
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16G UCIe Standard PHY for TSMC N5A Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
70
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16G UCIe Standard PHY for TSMC N7
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
71
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UALink PHY + Controller
INNOSILICON™ introduces its UALink PHY and Controller IP, purpose-built for the AI era’s high-performance chip design needs. This solution is fully co...
72
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UCIe 2.0 PHY for Standard Package (2nm)
The UCI Express Specification Revision 3.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, 24GT/s, 32GT/s, 48GT...
73
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UCIe Controller for Streaming Protocols
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...
74
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UCIe PHY IP on TSMC N3P
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
75
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UCIe PHY on Samsung SF5A
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...
76
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UCIe PHY on TSMC N3E
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...
77
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UCIe Protocol Layer: AXI-S
The AXI-S Protocol Layer for UCIe is a protocol adapter layer between a Streaming AXI Bus and the FDI interface of the UCIe D2D Adapter. It allows for...
78
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UCIe Standard Package PHY on Samsung S14LPP
The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...
79
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UCIe Standard Package PHY on Samsung S8LPU
The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...
80
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UCIe-A PHY for Advanced Package (x64) in Samsung (SF2)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
81
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UCIe-A PHY for Advanced Package (x64) in Samsung (SF4X)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
82
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UCIe-A PHY for Advanced Package (x64) in TSMC (N5)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
83
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UCIE-A PHY, 5nm/4nm
The InPsytech (IPT) UCIe-A PHY is a mass-production proven, state-of-the-art physical layer interface designed to provide exceptional performance and ...
84
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UCIE-A PHY, ADVANCED PACKAGE
The InPsytech (IPT) UCIe-A PHY is a state-of-the-art physical layer interface, offering industry-leading power efficiency and proven in mass productio...
85
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UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
86
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UCIe-S PHY for Standard Package (x32) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
87
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Chiplet Solution
Based on the traditional advantages of SerDes and DDR IP, KNiulink Semiconductor has launched a solution that meets the UCIe standard based on local r...
88
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Die-to-Die PHY
Eliyan uses its NuLink technology to develop die-to-die PHY IP products to support multiple standards (including UCIe and BoW) and multiple packaging ...
89
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GLink AXI Wrapper
GLink (GLink-fs 2.x + PCS-replay) AXI Wrapper is a digital IP designed to support AMBA AXI3/AXI4 compliant bus of user interface and provide data bus ...
90
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GLink CXS-Bridge
GLink (GLink-fs 2.x + PCS-replay) CXS-Bridge is a digital IP to interconnect between two dies that use Glink as a physical layer and provides AMBA CXS...
91
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GLink Multi-Slice PCS
GLink Multi-Slice PCS (IGDD2D004A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure consistent data arrivin...
92
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GLink Multi-Slice PCS
GLink Multi-Slice PCS (IGPD2D001A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure consistent data arrivin...
93
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Blumind Chiplet
Contact us to learn more about Neural Signal Processor known-good-die for system in package integration....
94
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Universal Chiplet Interconnect Express PHY IP GlobalFoundries® 22FDX®
The Racyics UCIe PHY is an energy-efficient chiplet interconnect IP solution for consumer and automotive applications. Implemented in 22FDX technology...
95
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Interface Controller - PHY IP
The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...
96
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Low Power Dual PHY for UCIe low cost robust Chiplets
YorChip UniPHY™ Dual PHY is a flexible version of YorChip’s multi-protocol PHY which supports UCIe and BOW standards. The Dual PHY’s unique feature ...
97
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Low Power Dual PHY for UCIe low cost robust Chiplets
YorChip UniPHY™ Dual PHY is a flexible version of YorChip's multi-protocol PHY which supports UCIe and BOW standards. The Dual PHY's uni...
98
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IPT 64GT/S UCIE-A PHY
The UCIe-A_HS 64Gbps Die-to-Die (D2D) PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects between...
99
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IPT 64GT/S UCIE-S PHY,
The high-speed UCIe-S 64G is a cutting-edge standard package die-to-die (D2D) and chiplet-to-chiplet (C2C) interface IP solution designed to enable ul...
100
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IPT D2D CONTROLLER
The InPsytech high-speed D2D Controller IP, optimized for power and latency enables die-to-die or chiplet-to-chiplet connectivity in applications like...