Design & Reuse
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7 IP
1
20.0
Die-2-die interfaces for chiplets - GPIOs for 2.5D and 3D integration
Analog I/O and on-chip Electrostatic Discharge (ESD) protection. Proven on many foundries: TSMC, UMC, GF, TowerSemi, Samsung Foundry, ... Proven in ...
2
5.0556
600Mbps Low Power D2D Interface in TSMC 16nm
Custom die-to-die interface in 16nm process technology. The I/O cell is bi-directional and has two modes of operation: standard rail-to-rail swing or ...
3
5.0556
<4Gbps Low Power D2D Interface in TSMC 12/16nm
Custom die-to-die interface in 12/16nm process technology. The I/O cells are defined as TX only, and RX only and have two modes of operation, standard...
4
5.0556
<4Gbps Low Power D2D Interface in TSMC 28nm
Custom die-to-die high-speed interface in 28nm process technology. The I/O cells are defined as TX only, and RX only, and have two modes of operation,...
5
0.0
Chiplet Solution
Based on the traditional advantages of SerDes and DDR IP, KNiulink Semiconductor has launched a solution that meets the UCIe standard based on local r...
6
0.0
Die-to-Die PHY
Eliyan uses its NuLink technology to develop die-to-die PHY IP products to support multiple standards (including UCIe and BoW) and multiple packaging ...
7
0.0
Blumind Chiplet
Contact us to learn more about Neural Signal Processor known-good-die for system in package integration....