Design & Reuse
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9 IP
1
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1 - 33Gbps PCIe Gen1-5 SerDes PHY (AXLinkIO MR)
The AXLinkIO MR IP utilizes the silicon-proven AXLinkIO transceiver architecture for medium-reach and PCIe type of channel links....
2
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1-56G-PCIe Gen5 ePHY Multi-Protocol SerDes IP - 7nm Low Power and Latency
Ultra-high speed SerDes IP, adopted by global Tier-1 network/storage/5G OEMs and major semiconductor companies. eTopus is the pioneer on PAN4 ADC/DSP...
3
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RAMLinx interconnect
RAM of any size and kind in your EFLX® array Many applications like DSP benefit from blocks of RAM distributed in the array. Of course it is possi...
4
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Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Mem...
5
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PCIe Controller IP
The Wolley PCI Express® (PCIe®) Controller IP is a highly configurable, performance-optimized core designed for ASIC and FPGA integration. Supporting ...
6
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Highly configurable Interlaken ILA & ILK
Tamba Networks offers a highly configurable Interlaken ILA and ILK core. The core is compliant with the Interlaken and Interlaken look-aside specifica...
7
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FlexNoC Resilience Package
For complex SoCs in advanced process nodes, CPU duplication and memory protection logic are no longer sufficient to address all the metrics required t...
8
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CXL (Compute eXpress Link) 3.1 IP
The Panmnesia Compute Express Link (CXL) IP implements all necessary logic for CXL device, host, and switch. The IP supports all features of the CXL 3...
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CXL Controller IP
The Wolley Compute Express Link® (CXL®) 3.1 controller is a highly-configurable design for ASIC and FPGA implementations. It maintains backward compat...