Design & Reuse
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7 IP
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Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Mem...
2
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PCIe 5.0 Controller IP
The Wolley PCI Express® (PCIe®) Controller IP is a highly configurable, performance-optimized core designed for ASIC and FPGA integration. Supporting ...
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PCIe 6.0 Controller IP
The Wolley PCI Express® (PCIe®) Controller IP is a highly configurable, performance-optimized core designed for ASIC and FPGA integration. Supporting ...
4
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Highly configurable Interlaken ILA & ILK
Tamba Networks offers a highly configurable Interlaken ILA and ILK core. The core is compliant with the Interlaken and Interlaken look-aside specifica...
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FlexNoC Resilience Package
For complex SoCs in advanced process nodes, CPU duplication and memory protection logic are no longer sufficient to address all the metrics required t...
6
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CXL (Compute eXpress Link) 3.1 IP
The Panmnesia Compute Express Link (CXL) IP implements all necessary logic for CXL device, host, and switch. The IP supports all features of the CXL 3...
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CXL Controller IP
The Wolley Compute Express Link® (CXL®) 3.1 controller is a highly-configurable design for ASIC and FPGA implementations. It maintains backward compat...