Design & Reuse
21 IP
1
140.0
InfiniNoC Interconnect
InfiniNoC is a highly customizable Network-on-Chip (NoC) from InfiniNode Technologies, designed to provide a scalable, high-performance communication ...
2
45.0
Ncore 3 Coherent Network-on-Chip (NoC)
For scalable and area-efficient heterogeneous cache coherent systems. The Arteris Ncore Cache Coherent Interconnect IP offers unparalleled scalabil...
3
44.0
FlexNoC 5 Option For Scalability and Performance Critical Systems
Arteris IP FlexNoC Performance Option accelerates development of next-generation deep neural network (DNN) and machine learning systems. Automate and ...
4
40.0
Coherent Network-on-chip (NoC) IP
C-NoC is a layered, scalable, configurable, and physically aware configurable NoC. It supports mesh, grid and torus topologies with simultaneous exist...
5
40.0
Non-coherent Network-on-chip (NoC) IP
NC-NoC is a layered, scalable, physically aware configurable NoC supporting multiple clocking schemes for SoCs that do not require coherency. NC-NoC s...
6
15.0
Coherent Network-on-Chip (NoC)
SkyeChip's NoC is the first in the world that is able to reconfigure routing paths after tapeout. It is a scalable and area efficient interconnect sol...
7
10.0
Mobiveil RapidIO Controller (GRIO)
Mobiveil Generic RapidIO (GRIO) controller is a highly flexible and configurable IP to provide RapidIO interface on one side and a generic interface o...
8
7.0
Non-Coherent Network-on-Chip (NoC)
SkyeChip's NoC is the first in the world that is able to reconfigure routing paths after tapeout. Performance (throughput and latency) optimized no...
9
5.0
High speed NoC (Network On-Chip) Interconnect IP
OPENEDGES is the only total memory system IP company providing both memory controller and on-chip interconnect. OIC is the ORBIT high-speed On-chip In...
10
0.0
5/10/40G Ultra Low Latency MAC PCS with AXI-4 and UCIe support
This IP is optimized for AI/ML workloads and lowest possible latency.It is not meant to be a generic 1G to 10G MAC – it only supports 5G and 10G...
11
0.0
Network Interconnect IP
The Network Interconnect (NIC) IP is a silicon proven and highly scalable on-chip communication fabric, enabling seamless connectivity between CPUs, G...
12
0.0
FlexNoC 5 Network-on-Chip (NoC)
Arteris FlexNoC 5 network-on-chip (NoC) physically aware interconnect IP improves development time, performance, power consumption, and die size of sy...
13
0.0
FlexNoC Resilience Package
For complex SoCs in advanced process nodes, CPU duplication and memory protection logic are no longer sufficient to address all the metrics required t...
14
0.0
FlexWay Interconnect IP
FlexWay 5 from Arteris is an essential entry-level IP generator for cost-efficient, high-performance network-on-chip (NoC) designs. It revolutionizes ...
15
0.0
Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
iNoCulator is a cloud-active EDA tool that is used to define the topology of a NoC quickly and easily, configure its parameters and simulate it to mea...
16
0.0
Ultra Accelerator Link(UALink) Controller
Full-stack, scalable, configurable UALink Transaction Layer (TL), Data Link Layer (DL), and Physical Layer (PL), interconnect IP for next-generation A...
17
0.0
Interconnect fabric IP with cache coherence support
StarNoC-500 is StarFive's first self-developed interconnect fabric IP with cache coherence support, supporting the construction of multi-cores and SoC...
18
0.0
Interconnect fabric IP with cache coherence support
StarNoC-700 is StarFive's self-developed high-scalable, high-performance interconnect fabric IP supporting cache coherence, enabling the construction ...
19
0.0
Interconnect Technology
EXTOLL introduces a new interconnection network architecture for High-Performance Computing, which brings a rich set of features to the HPC applicatio...
20
0.0
NoC Generator
A web-based NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs...
21
0.0
CodaCache Last Level Cache IP
CodaCache is a configurable, standalone, non-coherent cache IP that delivers unique business value through its advanced last-level cache (LLC) archite...