Design & Reuse
arrow Chip to Chip (6)
arrow Die-to-die (33)
arrow Intra SoC Connectivity (9)
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66 IP
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Interconnect fabric IP with cache coherence support
StarNoC-500 is StarFive's first self-developed interconnect fabric IP with cache coherence support, supporting the construction of multi-cores and SoC...
52
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Interconnect fabric IP with cache coherence support
StarNoC-700 is StarFive's self-developed high-scalable, high-performance interconnect fabric IP supporting cache coherence, enabling the construction ...
53
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Interconnect Technology
EXTOLL introduces a new interconnection network architecture for High-Performance Computing, which brings a rich set of features to the HPC applicatio...
54
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NoC Generator
A web-based NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs...
55
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CodaCache Last Level Cache IP
CodaCache is a configurable, standalone, non-coherent cache IP that delivers unique business value through its advanced last-level cache (LLC) archite...
56
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Low Power Dual PHY for UCIe low cost robust Chiplets
YorChip UniPHY™ Dual PHY is a flexible version of YorChip's multi-protocol PHY which supports UCIe and BOW standards. The Dual PHY's uni...
57
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XPHY Low power Chip to Chip SerDes IP, Silicon Proven in ST 28FDSOI
These IPs are targeted at applications requiring high speed, high bandwidth, low-power consumption, and low-latency interfaces....
58
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IPT 64GT/S UCIE-A PHY
The UCIe-A_HS 64Gbps Die-to-Die (D2D) PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects between...
59
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IPT 64GT/S UCIE-S PHY,
The high-speed UCIe-S 64G is a cutting-edge standard package die-to-die (D2D) and chiplet-to-chiplet (C2C) interface IP solution designed to enable ul...
60
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IPT D2D CONTROLLER
The InPsytech high-speed D2D Controller IP, optimized for power and latency enables die-to-die or chiplet-to-chiplet connectivity in applications like...
61
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IPT LOW POWER UCIE-A PHY
The Ultra-low power UCIe-A Die-to-Die PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-low-power system demand with up...
62
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IPT UCIE-S PHY
The IPT UCIe-S is a cutting-edge standard package die-to-die (D2D) and chiplet-to-chiplet (C2C) interface IP solution designed to enable high-speed an...
63
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Bunch of Wires [BoW] PHY IP
Blue Cheetah's Bunch of Wires [BoW] PHY IP design incorporates the maximum benefit of the Open Compute Project's (OCP) inter-chiplet PHY spec...
64
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Nutcracker XSR Connectivity Chiplet
Core and analog logic may not always deploy at the same time in the same process. Maturing high performance analog typically takes longer in moving to...
65
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CXL (Compute eXpress Link) 3.1 IP
The Panmnesia Compute Express Link (CXL) IP implements all necessary logic for CXL device, host, and switch. The IP supports all features of the CXL 3...
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CXL Controller IP
The Wolley Compute Express Link® (CXL®) 3.1 controller is a highly-configurable design for ASIC and FPGA implementations. It maintains backward compat...