Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Chip to Chip (31)
arrow Die-to-die (114)
arrow Intra SoC Connectivity (27)
172 IP
51
10.0
Chip-to-Chip IO Buffer - TSMC CLN5A
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
52
10.0
Chip-to-Chip IO Buffer - TSMC CLN6FF
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
53
10.0
Chip-to-Chip IO Buffer - TSMC CLN7FF
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
54
10.0
Die-to-Die Controller IP
The Synopsys Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accele...
55
10.0
Die-to-Die, 112G Ultra-Extra Short Reach PHY in GF (12nm)
The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...
56
10.0
Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5)
The Synopsys XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip modul...
57
10.0
Mobiveil RapidIO Controller (GRIO)
Mobiveil Generic RapidIO (GRIO) controller is a highly flexible and configurable IP to provide RapidIO interface on one side and a generic interface o...
58
9.0
IPT UCIE 2.0 CONTROLLER
High-Performance UCIe Controller IP for AI, Data Center & Consumer Applications The InPsytech UCIe 2.0 (Universal Chiplet Interconnect Express) Contr...
59
8.0
TSMC CLN5FF Glink 2.0 Die-to-Die PHY
IGAD2DY01A is a high speed die-to-die interface PHY which transmits data through TSMC advanced packaging solutions：Integrated Fan-Out (InFO) with RDL ...
60
7.0
Non-Coherent Network-on-Chip (NoC)
SkyeChip's NoC is the first in the world that is able to reconfigure routing paths after tapeout. Performance (throughput and latency) optimized no...
61
6.0
CHI NIC IP
The CHI Network Interconnect (CHI NIC) is a scalable, high-performance interconnect IP designed to connect processors, memory subsystems, and peripher...
62
6.0
CHI NOC IP
The CHI-based mesh interconnect is a scalable, high-performance communication fabric designed to connect a large number of nodes in modern SoC archite...
63
6.0
NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
Truechip's NoC Silicon IP provides chip designers and architects with an efficient way to connect multiple TileLink based master and slave devices wit...
64
6.0
Multi-Protocol NIC IP
The Network Interconnect (NIC) is a scalable, high-performance IP designed to connect processors, memory controllers, accelerators, and peripheral sub...
65
6.0
Multi-Protocol NoC IP
The mesh interconnect is a scalable, high-performance communication fabric designed to connect a large number of components in modern SoC architecture...
66
6.0
AXI NIC IP
The AXI Network Interconnect (AXI NIC) is a scalable, high-performance IP for connecting processors, memory controllers, and peripherals in modern SoC...
67
6.0
AXI NoC IP
The mesh interconnect is a scalable, high-performance communication fabric designed to connect a large number of master and slave devices in complex S...
68
5.0
UF16 D2D: <4Gbps low-power die-to-die interface, TSMC 16nm
A silicon-proven, low-power die-to-die interface in TSMC 16nm (FFC/FFC+) for flip-chip / multi-die assembly. Separate TX-only and RX-only cells run in...
69
5.0
SPI Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
70
5.0
SPI Slave Controller (SPI2APB, SPI2AXI, SPI2AHB Bus)
The Digital Blocks DB-SPI-S-AMBA-BRIDGE is a Serial Port Interface (SPI) Controller Verilog IP Core supporting SPI Slave Interface to APB Master Bus. ...
71
5.0
VX16: 600Mbps low-power D2D interface, TSMC 16nm FFC/FFC+
A custom, low-power die-to-die interface in TSMC 16nm FFC/FFC+. The bidirectional I/O cell (VX_HSIO) runs in two modes: standard full rail-to-rail swi...
72
2.0
I3C Master / Slave Controller - MIPI Basic v1.0
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – BASIC ...
73
1.0
UD28: <4gnps low-power die-to-die interface, TSMC 28nm
A silicon-proven, low-power die-to-die interface in TSMC 28nm (HPM/HPC/HPC+) for flip-chip / multi-die assembly. Separate TX-only and RX-only cells ru...
74
0.0
5/10/40G Ultra Low Latency MAC PCS with AXI-4 and UCIe support
This IP is optimized for AI/ML workloads and lowest possible latency.It is not meant to be a generic 1G to 10G MAC &ndash; it only supports 5G and 10G...
75
0.0
40G Ultralink D2D PHY for GLOBALFOUNDRIES
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity. The Cadence® UltraLin...
76
0.0
40G Ultralink D2D PHY for Samsung
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity. The Cadence® UltraLin...
77
0.0
40G Ultralink D2D PHY for TSMC
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity. The Cadence® UltraLin...
78
0.0
40G Ultralink D2D PHY for TSMC N3P
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
79
0.0
40G Ultralink D2D PHY for TSMC N5P
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
80
0.0
40G Ultralink D2D PHY for TSMC N6, N7
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
81
0.0
D2D (Die-to-Die) Interconnect IP in WhiteBox, Unlimited Usage
This die-to-die interconnect IP Core is defined as an AIB IP Core, which is optimized for 32-bit AXI data transfer, enabling Master-to-Slave AXI trans...
82
0.0
D2D PHY, ADVANCED PACKAGE, 3nm
The InPsytech (IPT) D2D PHY IP is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed...
83
0.0
D2D PHY, ADVANCED PACKAGE, 5nm/4nm
The InPsytech (IPT) D2D PHY is a mass-production proven, state-of-the-art physical layer interface designed to provide exceptional performance and eff...
84
0.0
D2D PHY, ADVANCED PACKAGE, 7nm/6nm
The InPsytech (IPT) D2D PHY is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed da...
85
0.0
D2D PHY, STANDARD PACKAGE, 7nm/6nm
The InPsytech (IPT) D2D PHY is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed da...
86
0.0
32G UCIe Standard PHY for TSMC N3P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
87
0.0
I3C Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...
88
0.0
I3C Master Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...
89
0.0
I3C Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-S-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improve...
90
0.0
16G UCIe Advanced PHY for Intel
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
91
0.0
16G UCIe Advanced PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
92
0.0
16G UCIe Advanced PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
93
0.0
16G UCIe Advanced PHY for TSMC N3P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
94
0.0
16G UCIe Advanced PHY for TSMC N4P/N5P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
95
0.0
16G UCIe Standard PHY for Samsung
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
96
0.0
16G UCIe Standard PHY for Samsung SF5A
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
97
0.0
16G UCIe Standard PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
98
0.0
16G UCIe Standard PHY for TSMC Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
99
0.0
16G UCIe Standard PHY for TSMC N3A Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
100
0.0
16G UCIe Standard PHY for TSMC N4P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...