Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Chip to Chip (24)
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156 IP
51
9.0308
UCIe 2.0 PHY for Standard Package (8nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, and 24GT/s with a 64...
52
9.0
IPT UCIE 2.0 CONTROLLER
High-Performance UCIe Controller IP for AI, Data Center & Consumer Applications The InPsytech UCIe 2.0 (Universal Chiplet Interconnect Express) Contr...
53
8.5077
UCIe 2.0 PHY for Advanced Package (4nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, 24GT/s and 32GT/s wi...
54
8.5077
UCIe 2.0 PHY for Advanced Package (8nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, and 24GT/s with a 64...
55
8.5077
UCIe 2.0 PHY for Standard Package (4nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, and 16GT/s with a 16-lane co...
56
8.5077
UCIe 2.0 PHY for Standard Package (5nm)
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, and 16GT/s with a 16-lane co...
57
8.5077
UCIe Controller for Standard Package
UCIe v2.0 controller implements the D2D Adapter defined in the UCIe 2.0 specification, as well as AXI4-to-Flit protocol conversion. The D2D Adapter su...
58
8.0
TSMC CLN5FF Glink 2.0 Die-to-Die PHY
IGAD2DY01A is a high speed die-to-die interface PHY which transmits data through TSMC advanced packaging solutions：Integrated Fan-Out (InFO) with RDL ...
59
7.0
Non-Coherent Network-on-Chip (NoC)
SkyeChip's NoC is the first in the world that is able to reconfigure routing paths after tapeout. Performance (throughput and latency) optimized no...
60
5.0
UF16 D2D: <4Gbps low-power die-to-die interface, TSMC 16nm
A silicon-proven, low-power die-to-die interface in TSMC 16nm (FFC/FFC+) for flip-chip / multi-die assembly. Separate TX-only and RX-only cells run in...
61
5.0
SPI Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
62
5.0
SPI Slave Controller (SPI2APB, SPI2AXI, SPI2AHB Bus)
The Digital Blocks DB-SPI-S-AMBA-BRIDGE is a Serial Port Interface (SPI) Controller Verilog IP Core supporting SPI Slave Interface to APB Master Bus. ...
63
5.0
VX16: 600Mbps low-power D2D interface, TSMC 16nm FFC/FFC+
A custom, low-power die-to-die interface in TSMC 16nm FFC/FFC+. The bidirectional I/O cell (VX_HSIO) runs in two modes: standard full rail-to-rail swi...
64
2.0
I3C Master / Slave Controller - MIPI Basic v1.0
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – BASIC ...
65
1.0
UD28: <4gnps low-power die-to-die interface, TSMC 28nm
A silicon-proven, low-power die-to-die interface in TSMC 28nm (HPM/HPC/HPC+) for flip-chip / multi-die assembly. Separate TX-only and RX-only cells ru...
66
0.0
5/10/40G Ultra Low Latency MAC PCS with AXI-4 and UCIe support
This IP is optimized for AI/ML workloads and lowest possible latency.It is not meant to be a generic 1G to 10G MAC &ndash; it only supports 5G and 10G...
67
0.0
40G Ultralink D2D PHY for GLOBALFOUNDRIES
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity. The Cadence® UltraLin...
68
0.0
40G Ultralink D2D PHY for Samsung
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity. The Cadence® UltraLin...
69
0.0
40G Ultralink D2D PHY for TSMC
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity. The Cadence® UltraLin...
70
0.0
40G Ultralink D2D PHY for TSMC N3P
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
71
0.0
40G Ultralink D2D PHY for TSMC N5P
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
72
0.0
40G Ultralink D2D PHY for TSMC N6, N7
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
73
0.0
D2D (Die-to-Die) Interconnect IP in WhiteBox, Unlimited Usage
This die-to-die interconnect IP Core is defined as an AIB IP Core, which is optimized for 32-bit AXI data transfer, enabling Master-to-Slave AXI trans...
74
0.0
D2D PHY, ADVANCED PACKAGE, 3nm
The InPsytech (IPT) D2D PHY IP is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed...
75
0.0
D2D PHY, ADVANCED PACKAGE, 5nm/4nm
The InPsytech (IPT) D2D PHY is a mass-production proven, state-of-the-art physical layer interface designed to provide exceptional performance and eff...
76
0.0
D2D PHY, ADVANCED PACKAGE, 7nm/6nm
The InPsytech (IPT) D2D PHY is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed da...
77
0.0
D2D PHY, STANDARD PACKAGE, 7nm/6nm
The InPsytech (IPT) D2D PHY is a state-of-the-art physical layer interface designed to provide exceptional performance and efficiency in high-speed da...
78
0.0
32G UCIe Standard PHY for TSMC N3P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
79
0.0
I3C Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...
80
0.0
I3C Master Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...
81
0.0
I3C Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-S-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improve...
82
0.0
16G UCIe Advanced PHY for Intel
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
83
0.0
16G UCIe Advanced PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
84
0.0
16G UCIe Advanced PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
85
0.0
16G UCIe Advanced PHY for TSMC N3P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
86
0.0
16G UCIe Advanced PHY for TSMC N4P/N5P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
87
0.0
16G UCIe Standard PHY for Samsung
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
88
0.0
16G UCIe Standard PHY for Samsung SF5A
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
89
0.0
16G UCIe Standard PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
90
0.0
16G UCIe Standard PHY for TSMC Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
91
0.0
16G UCIe Standard PHY for TSMC N3A Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
92
0.0
16G UCIe Standard PHY for TSMC N4P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
93
0.0
16G UCIe Standard PHY for TSMC N5A Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
94
0.0
16G UCIe Standard PHY for TSMC N7
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
95
0.0
UALink PHY + Controller
INNOSILICON™ introduces its UALink PHY and Controller IP, purpose-built for the AI era’s high-performance chip design needs. This solution is fully co...
96
0.0
UCIe 2.0 PHY for Standard Package (2nm)
The UCI Express Specification Revision 3.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, 24GT/s, 32GT/s, 48GT...
97
0.0
UCIe Controller for Streaming Protocols
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...
98
0.0
UCIe PHY IP on TSMC N3P
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
99
0.0
UCIe PHY on Samsung SF5A
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...
100
0.0
UCIe PHY on TSMC N3E
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...