Design & Reuse
arrow Chip to Chip (9)
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122 IP
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NoC Generator
A web-based NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs...
102
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CodaCache Last Level Cache IP
CodaCache is a configurable, standalone, non-coherent cache IP that delivers unique business value through its advanced last-level cache (LLC) archite...
103
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Coherent Network-on-chip (NoC) IP
C-NoC is a layered, scalable, configurable, and physically aware configurable NoC. It supports mesh, grid and torus topologies with simultaneous exist...
104
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Non-coherent Network-on-chip (NoC) IP
NC-NoC is a layered, scalable, physically aware configurable NoC supporting multiple clocking schemes for SoCs that do not require coherency. NC-NoC s...
105
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Low Power Dual PHY for UCIe low cost robust Chiplets
YorChip UniPHY™ Dual PHY is a flexible version of YorChip’s multi-protocol PHY which supports UCIe and BOW standards. The Dual PHY’s unique feature ...
106
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Low Power Dual PHY for UCIe low cost robust Chiplets
YorChip UniPHY™ Dual PHY is a flexible version of YorChip's multi-protocol PHY which supports UCIe and BOW standards. The Dual PHY's uni...
107
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XPHY Low power Chip to Chip SerDes IP, Silicon Proven in ST 28FDSOI
These IPs are targeted at applications requiring high speed, high bandwidth, low-power consumption, and low-latency interfaces....
108
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IPT 64GT/S UCIE-A PHY
The UCIe-A_HS 64Gbps Die-to-Die (D2D) PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects between...
109
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IPT 64GT/S UCIE-S PHY,
The high-speed UCIe-S 64G is a cutting-edge standard package die-to-die (D2D) and chiplet-to-chiplet (C2C) interface IP solution designed to enable ul...
110
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IPT D2D CONTROLLER
The InPsytech high-speed D2D Controller IP, optimized for power and latency enables die-to-die or chiplet-to-chiplet connectivity in applications like...
111
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IPT LOW POWER UCIE-A PHY
The Ultra-low power UCIe-A Die-to-Die PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-low-power system demand with up...
112
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IPT UCIE-S PHY
The IPT UCIe-S is a cutting-edge standard package die-to-die (D2D) and chiplet-to-chiplet (C2C) interface IP solution designed to enable high-speed an...
113
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TSMC CLN3FFE GLink 2.3LL Die-to-Die PHY
IGPD2DZO1A is a high-speed Die-to-Die interface PHY that transmits data through TSMC advanced packaging solutions, Integrated Fan-Out (InFO) with the ...
114
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TSMC CLN5FF GLink 2.0 Die-to-Die PHY
IGPD2DY01A is a high-speed Die-to-Die interface PHY that transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL ...
115
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TSMC CLN5FF GLink 2.3LL Die-to-Die PHY
IGAD2DY04A is a high-speed die-to-die interface PHY which transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL...
116
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TSMC CLN5FF GLink GPIO
IGID2DY01A GLink GPIO is one of the GLink series IPs. It provides low speed (up to 500 MHz) connection between two dies without requiring any initiali...
117
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TSMC CLN5FF GLink-3D Die-to-Die Master PHY
IGAD2DY02A is a GLink-3D high speed die-to-die interface Master PHY. It is used to transmit data between dies and assembled using TSMC System on Integ...
118
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TSMC CLN6FF/7FF Die-to-Die Interface PHY
This IGAD2DX01A test report shows the functional and characterization test result of GUC Die-to-Die Interface PHY IP for 8 Gbps operation. For IP deta...
119
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TSMC CLN7FF GLink-3D Die-to-Die Slave PHY
IGAD2DX03A is a GLink-3D high speed die-to-die interface Slave PHY. It is used to transmit data between dies and assembled using TSMC System on Integr...
120
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XSR PHY for TSMC N5
The Synopsys USR/XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip m...
121
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Nutcracker XSR Connectivity Chiplet
Core and analog logic may not always deploy at the same time in the same process. Maturing high performance analog typically takes longer in moving to...
122
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Automotive-Compliant Synopsys UCIe Controller IP
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...