Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Chip to Chip (24)
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156 IP
151
0.0
eSPI Target RTL SystemVerilog IP
Digital Blocks' DB-eSPI-Target-AMBA is a fully synthesizable SystemVerilog IP Core conforming to the eSPI 1.6 Specification for Target (Slave) applica...
152
0.0
XSR PHY for TSMC N5
The Synopsys USR/XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip m...
153
0.0
Nutcracker XSR Connectivity Chiplet
Core and analog logic may not always deploy at the same time in the same process. Maturing high performance analog typically takes longer in moving to...
154
0.0
Automotive-Compliant Synopsys UCIe Controller IP
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...
155
0.0
AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
The Digital Blocks DB-SPI-FLASH-CTRL is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad SPI Flash...
156
0.0
Synopsys UCIe Controller IP for Automotive
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...