Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Chip to Chip (31)
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172 IP
151
0.0
IPT D2D CONTROLLER
The InPsytech high-speed D2D Controller IP, optimized for power and latency enables die-to-die or chiplet-to-chiplet connectivity in applications like...
152
0.0
IPT LOW POWER UCIE-A PHY
The Ultra-low power UCIe-A Die-to-Die PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-low-power system demand with up...
153
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IPT UCIE-S PHY
The IPT UCIe-S is a cutting-edge standard package die-to-die (D2D) and chiplet-to-chiplet (C2C) interface IP solution designed to enable high-speed an...
154
0.0
TSMC 5FF 112G VSR SerDes Whitebox IP
This 112G VSR SerDes PHY IP is a configurable Tx/Rx physical layer for high-density, very-short-reach serial links. The TSMC 5FF implementation suppor...
155
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TSMC 7FF 56G Medium-Reach SerDes Whitebox IP
This 56G SerDes PHY IP is a configurable Tx/Rx solution for medium-reach electrical channels in networking, computing, storage, and high-bandwidth SoC...
156
0.0
TSMC CLN3FFE GLink 2.3LL Die-to-Die PHY
IGPD2DZO1A is a high-speed Die-to-Die interface PHY that transmits data through TSMC advanced packaging solutions, Integrated Fan-Out (InFO) with the ...
157
0.0
TSMC CLN5FF GLink 2.0 Die-to-Die PHY
IGPD2DY01A is a high-speed Die-to-Die interface PHY that transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL ...
158
0.0
TSMC CLN5FF GLink 2.3LL Die-to-Die PHY
IGAD2DY04A is a high-speed die-to-die interface PHY which transmits data through TSMC advanced packaging solutions: Integrated Fan-Out (InFO) with RDL...
159
0.0
TSMC CLN5FF GLink GPIO
IGID2DY01A GLink GPIO is one of the GLink series IPs. It provides low speed (up to 500 MHz) connection between two dies without requiring any initiali...
160
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TSMC CLN5FF GLink-3D Die-to-Die Master PHY
IGAD2DY02A is a GLink-3D high speed die-to-die interface Master PHY. It is used to transmit data between dies and assembled using TSMC System on Integ...
161
0.0
TSMC CLN6FF/7FF Die-to-Die Interface PHY
This IGAD2DX01A test report shows the functional and characterization test result of GUC Die-to-Die Interface PHY IP for 8 Gbps operation. For IP deta...
162
0.0
TSMC CLN7FF GLink-3D Die-to-Die Slave PHY
IGAD2DX03A is a GLink-3D high speed die-to-die interface Slave PHY. It is used to transmit data between dies and assembled using TSMC System on Integr...
163
0.0
eSPI Controller RTL SystemVerilog IP
Digital Blocks' DB-eSPI-Controller-AMBA is a fully synthesizable SystemVerilog IP Core conforming to the eSPI 1.6 Specification for Controller (Master...
164
0.0
eSPI Controller/Target RTL SystemVerilog IP
Digital Blocks' DB-eSPI-Controller-Target-AMBA is a highly versatile, fully synthesizable SystemVerilog IP Core conforming to the eSPI 1.6 Specificati...
165
0.0
eSPI Target RTL SystemVerilog IP
Digital Blocks' DB-eSPI-Target-AMBA is a fully synthesizable SystemVerilog IP Core conforming to the eSPI 1.6 Specification for Target (Slave) applica...
166
0.0
XSR PHY for TSMC N5
The Synopsys USR/XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in multi-chip m...
167
0.0
ST 28FDSOI 1.125–15 Gbps Multi-Protocol SerDes IP
This 15G SerDes PHY IP provides Tx and Rx functions for networking standards including CEI-6G/11G SR/MR/LR, XFI/SFI, XAUI/CAUI, SGMII, QSGMII, and CR4...
168
0.0
ST 28FDSOI 32G Networking SerDes Whitebox IP
This 32G SerDes PHY IP is a configurable transmitter and receiver solution for CEI, Ethernet-oriented, optical-module, and proprietary serial links. T...
169
0.0
Nutcracker XSR Connectivity Chiplet
Core and analog logic may not always deploy at the same time in the same process. Maturing high performance analog typically takes longer in moving to...
170
0.0
Automotive-Compliant Synopsys UCIe Controller IP
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...
171
0.0
AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
The Digital Blocks DB-SPI-FLASH-CTRL is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad SPI Flash...
172
0.0
Synopsys UCIe Controller IP for Automotive
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...