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179 IP
151
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APS1V - Compact Implementation of the RISC-V RV32IMC ISA
Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveragi...
152
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FPS29V - Dual Issue Implementation of the RISC-V RV32IMAFC ISA
Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveragi...
153
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APS3V - Compact Implementation of the RISC-V RV32IMC ISA
Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveragi...
154
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APS5V - Compact Implementation of the RISC-V RV32IMAC ISA
Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveragi...
155
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FPS69V - Dual Issue Implementation of the RISC-V RV64GC ISA
Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveragi...
156
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CPU IP - Follows the RVA23 Profile, supports RVV1.0 and supports all extensions of Vector Crypto
StarFive Dubhe-83 CPU IP features a 10+ stage pipeline, 3-issue, and out-of-order pipeline, follows the RVA23 Profile, supports RV64GCBVH, supports RV...
157
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NS31A RISC-V 32bit CPU which supports ISO26262 ASIL D
RISC-V 32bit General Purpose Tiny Core ISO26262:2018 ASIL D compliant SEooC IP RISC-V Solution by Collaborating with Partners RISC-V 32bit General P...
158
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TT-Ascalon X Out-of-Order, Superscaler, RISC-V CPU
Tenstorrent’s TT-Ascalon X is an Out-of-Order, superscalar, 8-wide decode processor based on the RISC-V RVA23 profile, co-designed and optimized with ...
159
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Dual-issue Linux-capable RISC-V core
The A730 is a dual-issue, in-order, 64-bit application processor capable of running Linux. The core is compatible with the RISC-V RVA22 profile. The c...
160
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XuanTie C908
XuanTie C908 is the latest RISC-V processor of the XuanTie series launched by T-Head Semiconductor. It has adopted the RV64GCB[V] instruction and is c...
161
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Nuclei N100: Very tiny area 2-stage-pipeline processor for embedded applications
Entry-level 32-bit RISC-V core, one of the world's smallest RISC-V cores. Optimized for ultra-low power consumption and minimal area, targeting cost-s...
162
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Nuclei N200: Ultra-low-power 2-stage-pipeline processor for embedded applications
Mid-range 32-bit RISC-V core, the world's first general-purpose MCU based on RISC-V. Balancing power, performance and area, comparable to ARM Cortex-M...
163
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Nuclei N300: Low-power 3-stage-pipeline processor with DSP/FPU capable for embedded applications
High-performance 32-bit RISC-V core, Nuclei's most widely adopted, feature-rich embedded core. Suitable for complex real-time embedded applications, w...
164
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Nuclei N600(SMP): 32-bit high-efficiency 6-stage-pipeline processor with DSP/FPU capable for embedded and real-time applications
32-bit high-efficiency multi-core processor without MMU, based on the Nuclei 600 Series architecture, supporting 2–4 core SMP (Symmetric Multi-Process...
165
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Nuclei NI1000: AI-optimized high-performance processor with advanced vector extension (up to 4096-bit) for high-end AI and HPC applications
64-bit high-end high-throughput RISC-V core, belonging to Nuclei 1000 series with out-of-order execution architecture. It adopts 2/3/4/6-wide decode d...
166
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Nuclei NI900: AI-optimized high-performance processor with advanced vector extension (up to 1024-bit) for AI applications
64/32-bit high-performance RISC-V core, supporting single-core and cluster SMP configurations. Equipped with powerful VPU, FPU and crypto accelerators...
167
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Nuclei NS100: 32-bit ultra-low-power 2-stage-pipeline secure processor for EAL 5+ secure embedded applications
32-bit ultra-low-power RISC-V core, designed for ultra-low-power MCU, IoT and other low-power applications. With minimal hardware cost, simplified str...
168
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Nuclei NS300: 32-bit low-power 3-stage-pipeline secure processor for EAL 5+ secure embedded applications
32-bit security-enhanced low-power RISC-V core, evolved from Nuclei N300 with enhanced security features. A competitive rival to ARM SC300, combining ...
169
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Nuclei U600(SMP): 32-bit high-efficiency 6-stage-pipeline processor (with MMU) for Linux-capable applications
32-bit high-efficiency RISC-V core with MMU, belonging to Nuclei 600 Series. Comparable to ARM Cortex-A5/R5, supporting 32-bit Linux system, balancing...
170
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Nuclei U900(SMP): 32-bit high-efficiency 9-stage-pipeline processor (with MMU) for Linux-capable applications
32-bit high-performance RISC-V core with MMU, belonging to Nuclei 900 Series. Comparable to ARM Cortex-A35/A53, supporting 32-bit Linux system, dual-i...
171
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Nuclei UX600(SMP): 64-bit high-efficiency 6-stage-pipeline processor (with MMU) for Linux-capable applications
Entry-level 64-bit high-efficiency RISC-V core with MMU, belonging to Nuclei 600 Series. Comparable to ARM Cortex-A7/A9/A35, supporting 64-bit Linux s...
172
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Nuclei UX900(SMP): 64-bit high-efficiency 9-stage-pipeline processor (with MMU) for Linux-capable applications
64-bit high-performance RISC-V core with MMU, belonging to Nuclei 900 Series. Comparable to ARM Cortex-A35/A53/A55, dual-issue execution, supporting 6...
173
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Multi-core capable RISC-V processor with vector extensions and Intelligence Extensions
The SiFive Intelligence X280 is a multi-core capable RISC-V processor with vector extensions and SiFive Intelligence Extensions and is optimized for A...
174
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RV32EC_P2 Processor Core IP
IQonIC Works RV32EC_P2 Core is a 2-stage pipeline RISC-V processor core, designed to meet the needs of small, low-power embedded applications, running...
175
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RV32IC_P5 Processor Core IP
IQonIC Works RV32IC_P5 Core is a larger, 5-stage pipeline core RISC-V processor, designed to meet the needs of medium-scale embedded applications that...
176
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eVocore I8500
Best-in-Class Performance EfficiencyThe I8500 is an in-order multiprocessing system with best-in-class power efficiency for use in SoC applications. E...
177
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eVocore P8700
eVocore CPUs are the first MIPS products based on the RISC-V open instruction set architecture (ISA) standard. These multiprocessors have unique featu...
178
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SweRV EH1 Support Package
The SweRV EH1 Support package (SSP) contains everything needed to deploy a Western Digital SweRV EH1 core in an integrated circuit providing support f...
179
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Azurite Core Hub Generators
The Azurite Core Hub Generator utilizes InCore's FlexiCore™ Technology to build a highly parameterized and configurable Core-Hub™ Gene...