Design & Reuse
163 IP
151
0.0
APS3V - Compact Implementation of the RISC-V RV32IMC ISA
Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveragi...
152
0.0
APS5V - Compact Implementation of the RISC-V RV32IMAC ISA
Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveragi...
153
0.0
FPS69V - Dual Issue Implementation of the RISC-V RV64GC ISA
Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveragi...
154
0.0
NS31A RISC-V 32bit CPU which supports ISO26262 ASIL D
RISC-V 32bit General Purpose Tiny Core ISO26262:2018 ASIL D compliant SEooC IP RISC-V Solution by Collaborating with Partners RISC-V 32bit General P...
155
0.0
Dual-issue Linux-capable RISC-V core
The A730 is a dual-issue, in-order, 64-bit application processor capable of running Linux. The core is compatible with the RISC-V RVA22 profile. The c...
156
0.0
XuanTie C908
XuanTie C908 is the latest RISC-V processor of the XuanTie series launched by T-Head Semiconductor. It has adopted the RV64GCB[V] instruction and is c...
157
0.0
Multi-core capable RISC-V processor with vector extensions and Intelligence Extensions
The SiFive Intelligence X280 is a multi-core capable RISC-V processor with vector extensions and SiFive Intelligence Extensions and is optimized for A...
158
0.0
RV32EC_P2 Processor Core IP
IQonIC Works RV32EC_P2 Core is a 2-stage pipeline RISC-V processor core, designed to meet the needs of small, low-power embedded applications, running...
159
0.0
RV32IC_P5 Processor Core IP
IQonIC Works RV32IC_P5 Core is a larger, 5-stage pipeline core RISC-V processor, designed to meet the needs of medium-scale embedded applications that...
160
0.0
eVocore I8500
Best-in-Class Performance EfficiencyThe I8500 is an in-order multiprocessing system with best-in-class power efficiency for use in SoC applications. E...
161
0.0
eVocore P8700
eVocore CPUs are the first MIPS products based on the RISC-V open instruction set architecture (ISA) standard. These multiprocessors have unique featu...
162
0.0
SweRV EH1 Support Package
The SweRV EH1 Support package (SSP) contains everything needed to deploy a Western Digital SweRV EH1 core in an integrated circuit providing support f...
163
0.0
Azurite Core Hub Generators
The Azurite Core Hub Generator utilizes InCore's FlexiCore™ Technology to build a highly parameterized and configurable Core-Hub™ Gene...