Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow AMBA AHB / APB/ AXI (203)
arrow CXL (21)
arrow D2D (1)
arrow Gen-Z (6)
arrow HDMI (88)
arrow I2C (96)
arrow Interlaken (3)
arrow MIL-STD-1553 (3)
arrow MIPI (508)
arrow Multi-Protocol PHY (33)
arrow PCI (241)
arrow RapidIO (6)
arrow SAS (5)
arrow SATA (74)
arrow Serdes (106)
arrow Smart Card (3)
arrow USB (405)
arrow V-by-One (22)
arrow VESA (80)
arrow Other (36)
1940 IP
501
6.5077
MIPI C-PHY TRx 8Gsps (5nm)
The MIPI C-PHY IP supports data rates of up to 8Gsps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provides...
502
6.5077
MIPI C-PHY TRx 8Gsps / D-PHY TRx 9Gbps Combo PHY (4nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...
503
6.5077
MIPI C-PHY TRx(80-8000Msps) / MIPI D-PHY TRx(80-9000Mbps) Combo PHY (4nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...
504
6.5077
MIPI CSI-2 RX Controller
The Camera Serial Interface 2 (CSI-2) Receiver (RX) Controller is a digital core that implements all protocol functions defined in the MIPI Alliance S...
505
6.5077
MIPI CSI-2 TX Controller
The Cameta Serial Interface 2 (CSI-2) Transmitter (TX) Controller is a digital core that implements all protocol functions defined in the MIPI Allianc...
506
6.5077
MIPI D-PHY TRx 2.1Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
507
6.5077
MIPI D-PHY TRx (5nm)
The MIPI D-PHY IP is a hardmacro PHY for CSI RX or DSI TX. IO pads and ESD structures are included. Extensive built-in self test features such as loop...
508
6.5077
MIPI D-PHY TRx 2.1Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
509
6.5077
MIPI D-PHY TRx 2.5Gbps (11nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
510
6.5077
MIPI D-PHY TRx 2.5Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
511
6.5077
MIPI D-PHY TRx 2.5Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
512
6.5077
MIPI D-PHY TRx 2.5Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
513
6.5077
MIPI D-PHY TRx 2.5Gbps (28nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
514
6.5077
MIPI D-PHY TRx 4.5Gbps (5nm)
The MIPI D-PHY IP supports data rates of up to 4.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
515
6.5077
MIPI D-PHY TRx 4.5Gbps (8nm)
The MIPI D-PHY IP supports data rates of up to 4.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
516
6.5077
MIPI DSI-2 RX Controller
The Display Serial Interface 2 (DSI-2) Receiver (RX) Controller is a digital core that implements all protocol functions defined in the MIPI Alliance ...
517
6.5077
MIPI DSI-2 TX Controller
The Display Serial Interface 2 (DSI-2) Transmitter (TX) Controller is a digital core that implements all protocol functions defined in the MIPI Allian...
518
6.5077
USB Super Speed+ PHY (4nm)
The USB PHY IP consists of a hard macro PMA and soft macro PCS compliant with USB 3.2 specification, supporting SuperSpeed+ (10 Gbps) operation. This ...
519
6.5077
Multi-Standard SerDes PHY (4nm)
The MSS PHY IP consists of a hard macro PMA architecture supporting multi-standard NRZ signaling up to 20 Gbps, compliant with PCIe Gen4, DisplayPort ...
520
6.0
A 32Gbps SerDes PHY in GlobalFoundries 22FDX
This 32 Gbps SerDes PHY is implemented in GlobalFoundries 22FDX CMOS technology and provides a high-performance, protocol-agnostic serial interface fo...
521
6.0
I2C Controller IP
The TrueSilicon I2C Controller IP is a highly configurable and robust serial communication interface designed for seamless integration into modern Sys...
522
6.0
I2C Master/Slave Controller Core IP
I2C Master/Slave Controller core implements a bidirectional serial interface compatible with the NXP’s I2C bus specification and supports all transfer...
523
6.0
CAN Controller IP
The TrueSilicon CAN Controller IP is a robust communication interface designed for system-on-chip (SoC) architectures, enabling reliable message-based...
524
6.0
RapidIO PHY
RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture. The architecture addresses the nee...
525
6.0
AHB To PCI Wrapper
VinChip’s AHB to PCI wrapper can be used to verify AHB (AMBA) based systems on a PCI environment for ease of debugging the target hardware and it can ...
526
6.0
AHB2APB Bridge IP
Truechip's AHB2APB Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency...
527
6.0
CHI2AXI bridge IP
The CHI2AXI bridge is a high-performance protocol converter designed to enable seamless interoperability between CHI (Coherent Hub Interface) and AXI ...
528
6.0
TileLink2AXI Bridge IP
The TileLink2AXI Bridge is a synthesizable, high-performance IP designed to provide seamless interoperability between TileLink-based components and AM...
529
6.0
MIPI D-PHY Receiver with PPI
SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...
530
6.0
MIPI D-PHY Receiver with PPI
SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...
531
6.0
MIPI Rx D-PHY
...
532
6.0
Embedded Host Controller 1. 1
...
533
6.0
Embedded Host Controller 2.0
...
534
6.0
USB 1.1 Hub Controller
...
535
6.0
USB 1.1 Open Host Controller
...
536
6.0
USB 2.0 Device Controller (IF Certified)
...
537
6.0
USB 2.0 Host Controller (EHCI)
...
538
6.0
USB 2.0 PHY; SMIC 40nm LL
...
539
6.0
USB 2.0 PHY; SMIC 55nm LL
...
540
6.0
USB 3.0 Device
A USB 3.0 Device IP Core that provides high performance SuperSpeed USB connectivity in a small footprint solution for quick and easy implementation of...
541
6.0
USB based High Speed System Debug IP
Architecture Independent Design Supports any AMBA AHB based System Easily portable to other buses such as Avalon Standard USB 2.0 interface to th...
542
6.0
USB2.0 On-The-Go
VinChip’s USB 2.0 High Speed OTG controller is designed for flexibility and ease of use and facilitates implementation of a wide variety of applicatio...
543
6.0
AXI Expander IP
The Truesilicon AXI Expander Block is a configurable IP designed for AXIbased systems where the data width of the Master Interface (MI) is smaller tha...
544
6.0
AXI Splitter IP
The AXI Splitter is a configurable IP designed to enable seamless data width conversion in AMBA AXI-based systems. It is primarily used when a wide da...
545
6.0
AXI- Interconnect : Advanced Extensible Interface Bus IP
The AMBA AXI protocol is targeted at high-performance, high-frequency system designs and includes a number of features that make it suitable for high-...
546
6.0
AXI2APB Bridge
Truechip's AXI2APB IP provides chip designers and architects, an efficient way to connect AXI & APB based IPs with reduced latency, power, and area....
547
6.0
AXI2APB Bridge IP
The TrueSilicon's AXI to APB Bridge is a high-performance protocol converter IP designed to enable seamless communication between AXI master devices a...
548
6.0
AXI2CHI Bridge IP
The AXI2CHI bridge is a high-performance protocol converter that enables seamless integration between AXI (Advanced eXtensible Interface) and CHI (Coh...
549
6.0
AXI2TileLink Bridge IP
The AXI2TileLink Bridge is a high-performance, synthesizable IP designed to enable seamless interoperability between AMBA AXI-based subsystems and Til...
550
5.5077
112Gb/s PAM4 SERDES PHY (14nm)
The Ethernet PHY IP is used for CEI-112G applications and serializes 8b/10b encoded data for Gen1 and Gen2, as well as 128b/130b encoded data for Gen3...