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1931 IP
1901
0.0
AXI to APB Bridge IP
SmartDV’s AXI to APB Bridge IP enables seamless communication between high-performance AXI-based systems and simpler, lower-power APB peripherals. It ...
1902
0.0
AXI to APB Bus Bridge
The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one ...
1903
0.0
AXI to UCIe Bridge IP
SmartDV’s AXI to UCIe Bridge IP enables seamless integration between standard AMBA AXI-based SoC architectures and the emerging UCIe (Universal Chiple...
1904
0.0
AXI2APB Bridge
Truechip's AXI2APB IP provides chip designers and architects, an efficient way to connect AXI & APB based IPs with reduced latency, power, and area....
1905
0.0
AXI4 Memory Map to AXI4-Stream Bridge
Digital Blocks DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog RTL IP Core accepts AXI4 Memory Map address, control, and data input, converts the address to ...
1906
0.0
CXL 1.x Controller IP
SmartDV’s CXL (Compute Express Link) 1.x Controller IP enables high-speed, low-latency, and cache-coherent communication between CPUs, memory, and acc...
1907
0.0
CXL 2.0 Retimer
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...
1908
0.0
CXL 2.x Controller IP
SmartDV’s CXL (Compute Express Link) 2.0 Controller IP extends support for advanced memory pooling, switching, and persistent memory, enhancing scalab...
1909
0.0
CXL 3.0 Device Controller
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...
1910
0.0
CXL 3.0 Dual Mode Controller
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...
1911
0.0
CXL 3.0 Host Controller
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...
1912
0.0
CXL 3.0 IP
EMPOWER YOUR DESIGN WITH UNMATCHED CXL PERFORMANCE Highly advanced and versatile CXL Controller IP that empowers your design with unparalleled spee...
1913
0.0
CXL 3.0 Retimer
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...
1914
0.0
CXL 3.x Controller IP
SmartDV’s CXL (Compute Express Link) 3.x Controller IP brings high-speed, coherent connectivity with enhanced fabric capabilities—supporting memory-ce...
1915
0.0
CXL Controller IP
The Wolley Compute Express Link® (CXL®) 3.1 controller is a highly-configurable design for ASIC and FPGA implementations. It maintains backward compat...
1916
0.0
CXL to UCIe Bridge IP
SmartDV’s CXL to UCIe Bridge IP enables seamless interoperability between Compute Express Link (CXL) and Universal Chiplet Interconnect Express (UCIe)...
1917
0.0
CXS to UCIe Bridge IP
SmartDV’s CXS to UCIe Bridge IP enables seamless connectivity between chiplet-based designs and traditional SoC architectures by bridging AMBA CXS int...
1918
0.0
Synopsys 112G PHY for TSMC N7
Synopsys IP Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high perfor...
1919
0.0
Synopsys 224G Ethernet PHY IP for TSMC N3P
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
1920
0.0
Synopsys 32G PHY NCS for TSMC N5
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and ...
1921
0.0
Synopsys Auto-Grade MIPI D-PHY Tx for TSMC N7
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
1922
0.0
Synopsys MIPI C-PHY IP on TSMC N7
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1923
0.0
Synopsys MIPI C-PHY v1.2 D-PHY v2.1 for TSMC N4P
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1924
0.0
Synopsys MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes for TSMC N5
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1925
0.0
Synopsys PCIe 4.0 PHY IP for TSMC N7
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
1926
0.0
Synopsys PCIe 5.0 PHY IP for SF5
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
1927
0.0
Synopsys PCIe 7.0 PHY IP for SF4X
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...
1928
0.0
Synopsys PCIe 7.0 PHY IP for TSMC N3P
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...
1929
0.0
Synopsys USB-C 3.1/DP TX PHY for TSMC N4P
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...
1930
0.0
Synopsys USB4 PHY IP for TSMC N4P
The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...
1931
0.0
Type-C PHY
Innosilicon Type-C IP is composed of the physical layer and the PHY logic. The physical layer contains 4 data channels, an AUX channel and bias circui...
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