Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow AMBA AHB / APB/ AXI (186)
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arrow D2D (8)
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arrow HDMI (96)
arrow I2C (97)
arrow Interlaken (2)
arrow MIL-STD-1553 (3)
arrow MIPI (531)
arrow Multi-Protocol PHY (34)
arrow PCI (247)
arrow RapidIO (7)
arrow SAS (6)
arrow SATA (75)
arrow Serdes (108)
arrow Smart Card (7)
arrow UFS (8)
arrow USB (412)
arrow V-by-One (22)
arrow VESA (79)
arrow Other (71)
2025 IP
1901
0.0
USB2.0 OTG PHY in SMIC 0.13G
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1902
0.0
USB2.0 OTG PHY in SMIC 28HKC+
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1903
0.0
USB2.0 OTG PHY in SMIC 28HKD 0.9/1.8V
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1904
0.0
USB2.0 OTG PHY in SMIC 28HKD 0.9/2.5V
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1905
0.0
USB2.0 OTG PHY in SMIC 40NEF
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1906
0.0
USB2.0 OTG PHY in SMIC 40NLL
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1907
0.0
USB2.0 OTG PHY in SMIC 55EF
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1908
0.0
USB2.0 OTG PHY in SMIC 55NLL
Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design. ...
1909
0.0
USB3.2 PHY on Samsung S8LPU
This IP is a USB 3.2 Gen2x2 PHY IP which provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 20Gbps. The USB 3.2 Gen2x2 I...
1910
0.0
USB3.2 PHY on Samsung SF4X
This IP is a USB 3.2 Gen2x2 PHY IP which provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 20Gbps. The USB 3.2 Gen2x2 I...
1911
0.0
USB4 PHY - SS SF2, North/South Poly Orientation
The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...
1912
0.0
USB4 PHY IP for TSMC N3E
The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...
1913
0.0
USB4 v2.0 Verification IP
Truechip's USB4 Verification IP provides an effective & efficient way to verify the components interfacing with USB4 interface of an IP or SoC, Truech...
1914
0.0
DSC decoder IP
DSC decoder IP is compliant with standard VESA Display Stream Compression version 1.1/1.2/1.2a....
1915
0.0
MSC Microsecond Channel high-speed controller
The MSC-CTRL IP core implements a high-speed serial interface controller designed to connect a microcontroller or SoC to external power devices or sen...
1916
0.0
CSI2 RX; Camera Serial Interface, MIPI Compliant
The CSI2 Receiver IP Interfaces between Camera module which has the transmitter and the application processor. The CSI2 Receiver IP is fully compliant...
1917
0.0
CSI2 TX; Camera Serial Interface, MIPI Compliant
CSI2 – TX is part of HCL’s MIPI® compliant offerings. The CSI2 Transmitter IP supports Pixel Interface on the camera sensor side and the DPHY is suppo...
1918
0.0
HSIC PHY
The Innosilicon HSIC PHY is fully compliant with the High-Speed Inter-Chip Supplement to the USB 2.0 Specification. By stripping off all the legacy US...
1919
0.0
ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
The VESA DSC 1.1 Encoder IP Core for automotive displays implements a fully compliant VESA DSC 1.1 encoder. It contains additional safety features to ...
1920
0.0
USIM Master IP
SmartDV's USIM Master IP is a silicon-proven, fully featured Universal Subscriber Identity Module interface solution purpose-built for SoC designs req...
1921
0.0
USIM Slave IP
SmartDV's USIM Slave IP is a silicon-proven, fully featured Universal Subscriber Identity Module device interface solution purpose-built for SoC desig...
1922
0.0
TSMC 12FFC Lane-based 1.25 - 22.5 Gbps Enterprise Multi-Standard SerDes
The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include PCIe Gen1-Gen4, SAS-4 G1-G5 and a...
1923
0.0
TSMC CLN12FFC Lane-based 1.5 - 16 Gbps Enterprise Multi-Standard SerDes
The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include PCIe Gen1-Gen4,SAS-3 G1-G4, SATA-...
1924
0.0
TSMC CLN28HPC+ Derivative IP of IGASERT06A Enterprise Multi-Standard SerDes
The GUC's Quad-Lane EMS-XT PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include CEI-28G-VSR, CEI-25G...
1925
0.0
TSMC CLN7FF Lane-based 1.5 – 22.5 Gbps Enterprise Multi-Standard SerDes
The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include PCIe Gen1-Gen4, SAS-4 G1-G5 and a...
1926
0.0
TSMC N7FF 25.78125Gbps Enterprise SerDes
The receiver equalizes and recovers incoming serial data and de-serializes the data stream into selectable 32/40/64 bit-wide data bus. The transmitter...
1927
0.0
ISO 7816 based digital controller for integrated circuit card compliant with ETSI TS 102 221 and EMV 2000 standards
Smart card controller core is compliant to ISO 7816 3 specification. The core is a technology independent, fully synchronous design. The controller fu...
1928
0.0
ISO 7816 based Smart Card Reader IP
The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications. It provides a communication interface with a sm...
1929
0.0
DSP-Based 56G PAM4 SerDes PHY IP
ForestSemi builds high-performance connectivity IP for the next generation of AI, HPC and data-center systems. With deep SerDes, PHY, and semiconducto...
1930
0.0
eSPI & SPI Master Controller w/FIFO
The Digital Blocks DB-eSPI-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI)...
1931
0.0
eSPI & SPI Slave Controller w/FIFO
The Digital Blocks DB-eSPI-SPI-S-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI)...
1932
0.0
eSPI Controller IP
SmartDV's eSPI Controller IP is a silicon-proven, fully featured Enhanced Serial Peripheral Interface controller solution purpose-built for SoC design...
1933
0.0
xSPI Master IP
SmartDV's xSPI Master IP is a silicon-proven, fully featured eXtended Serial Peripheral Interface master solution purpose-built for SoC designs requir...
1934
0.0
QSPI Master IP
SmartDV's QSPI Master IP is a silicon-proven, high-performance Quad SPI flash memory controller purpose-built for SoC designs requiring flexible, high...
1935
0.0
eSPI Target IP
SmartDV's eSPI Target IP is a silicon-proven, fully featured Enhanced Serial Peripheral Interface target solution purpose-built for SoC designs requir...
1936
0.0
eSPI Target to LPC Bridge IP
SmartDV's eSPI Target to LPC Bridge IP is a silicon-proven, fully featured protocol bridge solution purpose-built for SoC designs requiring seamless c...
1937
0.0
HSSTP Link
The High-Speed Serial Trace Port (HSSTP) Controller IP implements the ARM HSSTP protocol. HSSTP replaces the existing parallel data output port, enab...
1938
0.0
HSSTP PHY TX (5nm) (1.5 Gbps, 3 Gbps, and 6 Gbps) SF5A
The HSSTP TX PHY is a 5nm hard macro supporting up to 6Gbps data rates with dual lanes and a hybrid mode driver for AC-coupled links. It includes feat...
1939
0.0
MST Topology Management Stack
The Trilinear Technologies DisplayPort Multi-stream Transport (MST) Topology Management Software enables developers to accelerate software development...
1940
0.0
ST 28FDSOI MIPI DigRF v1.0 Tx/Rx Whitebox PHY
This MIPI DigRF Tx/Rx PHY IP provides a bidirectional physical interface for connecting RFIC and digital-baseband subsystems. The design uses an M-PHY...
1941
0.0
OT9120 Simplified Integration Power Delivery Type-C Source IP
This OT9120 is an easy to integrate and configure Type-C source port with Power Delivery. It is delivered as RTL and an Analog Front End hard macro. N...
1942
0.0
OT9121 Simplified Integration Power Delivery Type-C Source IP
This OT9121 is an easy to integrate and configure Type-C sink port with Power Delivery. It is delivered as RTL and an Analog Front End hard macro. No ...
1943
0.0
JTAG Master IP
SmartDV's JTAG Master IP is a silicon-proven, fully featured boundary scan controller engineered for SoC designs requiring reliable, standards-complia...
1944
0.0
JTAG Slave IP
SmartDV's JTAG Slave IP is a silicon-proven, fully featured boundary scan solution engineered for SoC designs requiring reliable, standards-compliant ...
1945
0.0
JTAG Slave To AHB Bridge IP
SmartDV's JTAG Slave to AHB Bridge IP is a silicon-proven, high-performance debug and test access solution engineered for SoC designs requiring seamle...
1946
0.0
JTAG Slave To APB Bridge IP
SmartDV's JTAG Slave to APB Bridge IP is a silicon-proven, lightweight debug and test access solution engineered for SoC designs requiring seamless co...
1947
0.0
JTAG Slave To AXI Bridge IP
SmartDV's JTAG Slave to AXI Bridge IP is a silicon-proven, high-performance debug and test access solution engineered for SoC designs requiring seamle...
1948
0.0
Dual-Role Device Controller for USB 3.0
Mature solutions featuring xHCI Host, Device, and Dual-Role Certified for compliance with USB 3.0 Specification v1.0, and xHCI Specification v1.0, ...
1949
0.0
Dual-Role Device Controller for USB 3.1
Mature solutions featuring xHCI Host, Device, and Dual-Role Certified for compliance with USB 3.1 Specification v1.0, and xHCI Specification v1.0, ...
1950
0.0
Multi-Function PCI Master/Target Interface Core
The PCI-M32MF implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up...