Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow AMBA AHB / APB/ AXI (186)
arrow CXL (20)
arrow D2D (8)
arrow Gen-Z (6)
arrow HDMI (96)
arrow I2C (97)
arrow Interlaken (2)
arrow MIL-STD-1553 (3)
arrow MIPI (531)
arrow Multi-Protocol PHY (34)
arrow PCI (247)
arrow RapidIO (7)
arrow SAS (6)
arrow SATA (75)
arrow Serdes (108)
arrow Smart Card (7)
arrow UFS (8)
arrow USB (412)
arrow V-by-One (22)
arrow VESA (79)
arrow Other (71)
2025 IP
1951
0.0
Multi-Link Multi-Protocol SerDes 10Gbps in GF 28SLP
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
1952
0.0
Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 55LP
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
1953
0.0
Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 65GP
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
1954
0.0
Multi-Link Multi-Protocol SerDes 16Gbps in TSMC 28HPC
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
1955
0.0
Multi-Standard SerDes PHY (4nm) SF4X
The MSS PHY IP consists of a hard macro PMA architecture supporting multi-standard NRZ signaling up to 20 Gbps, compliant with PCIe Gen4, DisplayPort ...
1956
0.0
Multi-Video-Source Multiplexing Serial Video Transmitter for MIPI CSI2
The SVT-CS4AP2 supports MIPI CSI2 over MIPI D-PHY. It allows mutilplexing of up to 10 video sources into a CSI2 output stream...
1957
0.0
Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output
This IP multiplexes inputs from up to 4 CSI2 cameras, each with up to 4 data lanes, to a single CSI2 output stream, with up to 4 lanes. It comprises o...
1958
0.0
Multiprotocol 10G PHY in TSMC (16nm, N7)
The multi-lane Synopsys IP Multi-Protocol 10G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio, meeting the growing need...
1959
0.0
eUSB 2.0 PHY in TSMC (N5, N4P, N4C, N3P, N2P)
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
1960
0.0
eUSB 2.0 PHY in TSMC (N5A, N3A) for Automotive
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
1961
0.0
eUSB2 PHY
The industry’s most advanced process nodes do not support 3.3V signaling and 5V tolerance as required by the USB 2.0 specification. 3.3V signaling was...
1962
0.0
eUSB2 PHY on Samsung SF4X
The Embedded USB 2.0 PHY is a High speed System-on-Chip (SoC) integrated transceiver IP in advanced process that implements the Intel® UTMI standard. ...
1963
0.0
eUSB2v2 Controller
Proven solution featuring host and peripheral eUSB2V2 scales up to 4.8Gbps of data rate with the flexibility to configure asymmetrical or symmetric...
1964
0.0
eUSB2V2 PHY
Low voltage USB 2.0 supporting 4.8Gbps eUSB2V2 is primarily a performance enhancement to eUSB2 native mode to provide more bandwidth for peripherals,...
1965
0.0
eUSB2V2 PHY in TSMC (22nm)
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
1966
0.0
LVDS Tx IP, Silicon Proven SMIC 14SF+
The Low-Voltage Differential Signaling Transmitter IP Core provides a very High speed and Low power differential data transfer for Video interface and...
1967
0.0
AVSBus 1.x Master IP
SmartDV's AVSBus 1.x Master IP is a silicon-proven, fully featured Adaptive Voltage Scaling Bus master solution purpose-built for SoC, ASIC, and FPGA ...
1968
0.0
AVSBus 1.x Slave IP
SmartDV's AVSBus 1.x Slave IP is a silicon-proven, fully featured Adaptive Voltage Scaling Bus slave solution purpose-built for Point of Load voltage ...
1969
0.0
AVSBus 2.x Controller IP
SmartDV's AVSBus 2.x Master IP is a silicon-proven, fully featured Adaptive Voltage Scaling Bus master solution purpose-built for SoC, ASIC, and FPGA ...
1970
0.0
AVSBus 2.x Target IP
SmartDV's AVSBus 2.x Slave IP is a silicon-proven, fully featured Adaptive Voltage Scaling Bus slave solution purpose-built for Point of Load voltage ...
1971
0.0
AXI Bridge for PCIe IP Core
The AXI Bridge for PCIe IP core is the  IP solution with a powerful mix of multiple industry standard memory mapped AXI Interfaces.The AXI Bridge IP c...
1972
0.0
AXI Interconnect Fabric
The AXI Interconnect provides the necessary infrastructure to connect as many as 8 shared AXI Slaves to as many as 4 AXI Bus Masters. AXI defines 5...
1973
0.0
AXI Interface Core
Rambus’s AXI Interface Core is designed for use in applications requiring ARM’s Advanced eXtensible Interface (AXI). The core accepts write and rea...
1974
0.0
AXI Multilayer Interconnect
The AXI-MLIC is an AMBA® AXI bus interconnect fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The AXI fabric ...
1975
0.0
AXI Multilayer Interconnect IP
SmartDV's AXI Multilayer Interconnect IP is a silicon-proven, high-performance AMBA AXI bus fabric solution purpose-built for SoC designs requiring hi...
1976
0.0
AXI Subsystem
The AXI-SBS is an integrated, verified, AMBA® compliant hardware/software system ready for embedded applications using processors with AXI4 interfaces...
1977
0.0
AXI to AHB Bridge IP
SmartDV's AXI to AHB Bridge IP is a silicon-proven, fully featured protocol bridge solution purpose-built for SoC designs requiring seamless connectiv...
1978
0.0
AXI to AHB Lite Bus Bridge
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...
1979
0.0
AXI to APB Bridge
The AXI2APB implements a bridge between AXI and APB buses, allowing the connection of peripherals with an APB interface to an AXI bus. The highly con...
1980
0.0
AXI to APB Bridge IP
SmartDV's AXI to APB Bridge IP is a silicon-proven, fully featured protocol bridge solution purpose-built for SoC designs requiring seamless connectiv...
1981
0.0
AXI to APB Bus Bridge
The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one ...
1982
0.0
AXI to UCIe Bridge IP
SmartDV's AXI to UCIe Bridge IP is a silicon-proven, fully featured chiplet interconnect bridge solution purpose-built for SoC and multi-die system de...
1983
0.0
AXI2APB Bridge
Truechip's AXI2APB IP provides chip designers and architects, an efficient way to connect AXI & APB based IPs with reduced latency, power, and area....
1984
0.0
AXI4 Memory Map to AXI4-Stream Bridge
Digital Blocks DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog RTL IP Core accepts AXI4 Memory Map address, control, and data input, converts the address to ...
1985
0.0
CXL 1.x Controller IP
SmartDV's CXL 1.x Controller IP is a fully featured Compute Express Link solution purpose-built for SoC designs requiring high-bandwidth, cache-cohere...
1986
0.0
CXL 2.0 Retimer
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...
1987
0.0
CXL 2.x Controller IP
SmartDV's CXL 2.0 Controller IP is a fully featured Compute Express Link solution purpose-built for SoC designs requiring CXL switching, memory poolin...
1988
0.0
CXL 3.0 Device Controller
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...
1989
0.0
CXL 3.0 Dual Mode Controller
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...
1990
0.0
CXL 3.0 Host Controller
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...
1991
0.0
CXL 3.0 IP
EMPOWER YOUR DESIGN WITH UNMATCHED CXL PERFORMANCE Highly advanced and versatile CXL Controller IP that empowers your design with unparalleled spee...
1992
0.0
CXL 3.0 Retimer
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...
1993
0.0
CXL 3.x Controller IP
SmartDV's CXL 3.x Controller IP is a fully featured Compute Express Link solution purpose-built for SoC designs requiring fabric-scale coherent memory...
1994
0.0
CXL Controller
Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications The Cadence® Controller IP for CXL provides the logic...
1995
0.0
CXL Controller IP
The Wolley Compute Express Link® (CXL®) 3.1 controller is a highly-configurable design for ASIC and FPGA implementations. It maintains backward compat...
1996
0.0
CXL to UCIe Bridge IP
SmartDV's CXL to UCIe Bridge IP is a fully featured chiplet interconnect bridge solution purpose-built for SoC and multi-die system designs requiring ...
1997
0.0
CXS to UCIe Bridge IP
SmartDV's CXS to UCIe Bridge IP is a fully featured chiplet interconnect bridge solution purpose-built for SoC and multi-die system designs requiring ...
1998
0.0
Extended MIPI CSI2 Serial Video Receiver, 64 bits, 8 data lanes, 4 pixels/clock
Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps. This development requires high bandwidth betwe...
1999
0.0
Synopsys 112G PHY for TSMC N7
Synopsys IP Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high perfor...
2000
0.0
Synopsys 128G PHY IP for TSMC N4P
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...