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1891 IP
251
20.0
MIPI D-PHY Bidirectional 4 Lanes in Fujitsu (40nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
252
20.0
MIPI D-PHY Bidirectional 4 Lanes in GF (40nm, 28nm, 22nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
253
20.0
MIPI D-PHY Bidirectional 4 Lanes in SMIC (40nm, 28nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
254
20.0
MIPI D-PHY Bidirectional 4 Lanes in TSMC (40nm, 28nm, 16nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
255
20.0
MIPI D-PHY CSI-2 RX+ (Receiver) IP in TSMC 40LP
The MXL-DPHY-CSI-2-RX+-T-040LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard f...
256
20.0
MIPI D-PHY DSI RX (Receiver/Peripheral) in UMC 22ULP/22ULL
The MXL-DPHY-DSI-RX-U-22ULP-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificat...
257
20.0
MIPI D-PHY RX
Silicon Library's MIPI DPHY 1.2 Rx PHY IP supports data rates up to 1.5Gbps. This IP includes two PLLs. This silicon proven IP is available in variou...
258
20.0
MIPI D-PHY Rx-Only 2 Lanes in GF (28nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
259
20.0
MIPI D-PHY Rx-Only 2 Lanes in SMIC (40nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
260
20.0
MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
261
20.0
MIPI D-PHY Rx-Only 2 Lanes in UMC (28nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
262
20.0
MIPI D-PHY Rx-Only 4 Lanes in GF (28nm, 12nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
263
20.0
MIPI D-PHY Rx-Only 4 Lanes in SMIC (40nm, 28nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
264
20.0
MIPI D-PHY Rx-Only 4 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
265
20.0
MIPI D-PHY Rx-Only 4 Lanes in UMC (28nm, 22nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
266
20.0
MIPI D-PHY TX
Silicon Library's MIPI DPHY 1.2 Tx PHY IP supports data rates up to 1.5Gbps and 2.5Gbps per lane (in HS), depending on the technology node. This sili...
267
20.0
MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
268
20.0
MIPI D-PHY Tx-Only 4 Lanes in GF (12nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
269
20.0
MIPI D-PHY Tx-Only 4 Lanes in SMIC (28nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
270
20.0
MIPI D-PHY Tx-Only 4 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
271
20.0
MIPI D-PHY Tx-Only 4 Lanes in UMC (28nm, 22nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
272
20.0
MIPI D-PHY Universal IP in TSMC 28HPC+
The MXL-DPHY-UNIV-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificatio...
273
20.0
MIPI D-PHY/LVDS Combo CSI-2 RX (Receiver) in TSMC 28HPC+
The MXL-LVDS-DPHY-1p5G-CSI-2-RX-T-028HPC+ is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Spe...
274
20.0
MIPI DSI-2 controllers with VESA DSC for high-speed serial interface between application processor and displays
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...
275
20.0
MIPI DSI-2 host/device controllers for high-speed serial interface between application processor and displays
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...
276
20.0
MIPI I3C controller delivers high bandwidth and scalability for integration of multiple sensors
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...
277
20.0
MIPI M-PHY G4 Type 1 1Tx1RX in TSMC (16nm, 12nm, N5)
The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The I...
278
20.0
MIPI M-PHY G4 Type 1 2TX2RX in GF (12nm)
The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The I...
279
20.0
MIPI M-PHY G5 Type 1 2Tx2Rx in Samsung (14nm)
The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The I...
280
20.0
MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm)
MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pi...
281
20.0
MIPI UniPro IP for reliable, high-performance and low power link between devices in mobile devices
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...
282
20.0
IO 1.2V GPIO in Samsung (4nm)
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
283
20.0
IO 1.8V GPIO in Samsung (4nm)
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
284
20.0
IO 1.8V LVDS in GF (22nm)
Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...
285
20.0
IO 1.8V LVDS Rx in GF (12nm)
Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...
286
20.0
IO 3.3V eMMC in GF (22nm)
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...
287
20.0
IO 3.3V LVDS Rx in GF (12nm)
Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...
288
20.0
IO I2C 3.3V in GF (22nm)
Synopsys Inter-Integrated Circuit (I2C) I/O library is used for two wire interfaces to connect low-speed devices like EEPROM, A/D, and D/A converters ...
289
20.0
IO I3C 3.3V in GF (22nm)
Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...
290
20.0
IP Prototyping Kits for USB, DDR, MIPI, PCI Express protocols
The Synopsys IP Prototyping Kits, part of the IP Accelerated initiative, center around a complete, out-of-the-box reference design that consists of a ...
291
20.0
LPDDR4/3, DDR4/3 Memory Controller IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
292
20.0
Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market
Customers are increasingly utilizing third-party standards-based IP in their designs, but face several challenges. With more IP and more complex inter...
293
20.0
USB 3.0 PHY in TSMC (65nm, 55nm, 40nm, 28nm)
The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer a...
294
20.0
USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps. It is compl...
295
20.0
USB4 Gen3X2 and DP1.4 X4 PHY IP with Type-C connector support
M31 USB4 Gen3x2 transceiver IP provides a complete range of USB4 Gen3x2 host and peripheral applications up to 40Gbps. It is compliant with the PIPE5....
296
20.0
DSC Decoder
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has b...
297
20.0
DSC Encoder
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has b...
298
20.0
TSMC 4nm (N4P) 1.2V/1.8V Basekit Libraries
Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic librarie...
299
20.0
TSMC 4nm (N4P) 1.2V/1.8V Basekit Libraries, multiple metalstacks
Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic librarie...
300
20.0
TSMC 4nm (N4P) 1.2V/1.8V I3C Libraries
Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...