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1926 IP
251
20.0
TSMC 5nm (N5) 1.2V/1.8V Failsafe GPIO Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
252
20.0
TSMC 5nm (N5) 1.2V/1.8V Failsafe GPIO Libraries, multiple metalstacks
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
253
20.0
TSMC 5nm (N5) 1.2V/1.8V I3C Libraries
Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...
254
20.0
TSMC 5nm (N5) 1.2V/1.8V/2.5V Failsafe GPIO Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
255
20.0
TSMC 5nm (N5) 1.2V/1.8V/2.5V GPIO Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
256
20.0
TSMC 5nm (N5) 1.2V/1.8V/2.5V GPIO Libraries, multiple metalstacks
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
257
20.0
TSMC 5nm (N5) 1.8V SD/eMMC IO
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...
258
20.0
TSMC 5nm (N5) 1.8V SD/eMMC PHY
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...
259
20.0
TSMC 5nm (N5) 2.5V Basekit Libraries
Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...
260
20.0
TSMC 5nm (N5)1.8V SD/eMMC PHY, multiple metalstacks
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...
261
20.0
TSMC 6nm (6FF) 3.3V GPIO
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
262
20.0
TSMC 6nm (6FF) 3.3V SMBUS (I2C) IO
Synopsys Inter-Integrated Circuit (I2C) I/O library is used for two wire interfaces to connect low-speed devices like EEPROM, A/D, and D/A converters ...
263
20.0
TSMC 6nm (N6) 3.3V Basekit Libraries
Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic librarie...
264
20.0
TSMC 7nm (7FF) 1.8V LVDS
Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...
265
20.0
TSMC 7nm (7FF) 3.3V GPIO
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
266
20.0
eUSB 2.0 PHY IP
Arasan Chip Systems, the leading provider of IP for Mobile and Automobile SOC’s, presents its latest eUSB2 IP. Embedded USB2 (eUSB2) is a new generati...
267
20.0
CXL memory expansion
DenseMem increases effective CXL Type 3 Device memory capacity by a factor of 2x through transparent, in-line memory compression/decompression with mi...
268
20.0
Synopsys PCIe 4.0 PHY IP for TSMC N7
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
269
16.0
3.3V general purpose I/O for 28nm CMOS
The 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.8V thick oxide MOS devices. It ...
270
16.0
1.8V general purpose I/O for 4nm FinFET
The Sofics 1.8V capable GPIO is an IP macro for on-chip integration. It is a 1.8V general purpose I/O built with a stack of 1.2V MOS FINFET devices. I...
271
16.0
AHB-Lite APB4 Bridge
The Roa Logic AHB-Lite APB4 Bridge is a fully parameterized soft IP interconnect bridge between the AMBA 3 AHB-Lite v1.0 and AMBA APB v2.0 bus protoco...
272
16.0
AHB-Lite General Purpose Memory Module
The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master. All signals defi...
273
16.0
AHB-Lite Multilayer Switch
The Roa Logic AHB-Lite Multi-layer Interconnect is a fully parameterized High Performance, Low Latency Interconnect Fabric soft IP for AHB-Lite. It al...
274
16.0
AHB-Lite Timer
The Roa Logic AHB-Lite Timer IP is a fully parameterized soft IP implementing a user-defined number of timers and functions as specified by the RISC-V...
275
16.0
RISC-V Compliant Platform Level Interrupt Controller
Fully Parameterized & Programmable Platform Level Interrupt Controller (PLIC) for RISC-V based Processor Systems supporting a user-defined number of i...
276
16.0
APB4 General Purpose Input/Output Module
The APB4 GPIO Core is fully parameterised core designed to provide a user-defined number of general purpose, bidirectional IO to a design. The IO a...
277
16.0
APB4 Multiplexer
The AMBA APB v2.0 bus protocol – commonly referred to as APB4 – defines a low-cost interface that is optimized for minimal power consumption and redu...
278
16.0
USB2.0 Host Transceiver PHY
USB 2.0 HOST Transceiver is a fully integrated PHY Core which is a super-set of HOST PHY with High Speed (HS), Full-Speed (FS) and Low-Speed Transceiv...
279
15.0
3.3V general purpose I/O for 4nm FinFET
The Sofics 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.2V (1.5V overdrive) MOS ...
280
15.0
2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter
The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture of t...
281
15.0
120dB PDM-to-PCM Digital Microphone Interface
The AR36T05 is a soft macro low-power high-performance digital microphone interface modulator IP. The IP converts stereo/mono 1-bit pulse-density modu...
282
15.0
Camera SLVS-EC 3.0 Transmitter 10.0Gbps 8-Lane
* The CL12811M8TIP10000 TXPHY supports 8 TX DATA lanes for up to 10Gbps application. A wide range phase-locked clock is embedded in the IP to suppor...
283
15.0
PCIe 5.0 PHY
With sophisticated architecture and advanced technology, KNiulink SerDes PHY IP with PMA and PCS layer is designed for low power and high performance ...
284
15.0
High Performance Second Generation Extended MIPI CSI2 Receiver
Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps. This development requires high bandwidth betwe...
285
15.0
MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations. It complies with MIPI® CSI2 V2.0 and DPHY1.2 spec...
286
15.0
DP/eDP1.4b RX Controller
Silicon Library’ｓeDP/DP1.4b RX Controller works with PHY IPs by Silicon Library or customers' PHYs....
287
15.0
DP/eDP1.4b TX Controller
Silicon Library’ｓeDP/DP1.4b TX Controller works with PHY IPs by Silicon Library or customers' PHYs....
288
15.0
ASA-ML Serdes IP Core in 22nm
The ASA PHY IP Core in 22nm delivers next-generation automotive SerDes connectivity, enabling high-bandwidth, low-latency serial links for advanced au...
289
15.0
ASA-ML Serdes IP Core in 28nm
The ASA PHY IP Core in 28nm provides scalable and robust SerDes connectivity for advanced automotive SoCs. Supporting the Automotive SerDes Alliance s...
290
15.0
USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps
KA13UGUSB20ST001 is USB2.0 physical layer transceiver (PHY) integrated circuits. The PHY can be configured for either an 8-bit or a 16-bit parallel in...
291
15.0
TSMC 13.1Gbps Multi-Protocol Low-Power SerDes IP
It is a 4-lane Serializer/Deserializer IP supporting data rates from 500Mbps to 13.1Gbps. It features flexible architecture for multiple high-speed se...
292
15.0
TSMC 25Gbps SerDes IP with Equalizer
This is a high-performance, multi-protocol serial transceiver IP that supports data rates from 1Gbps to 26Gbps. Built on TSMC 12nm technology, it is d...
293
15.0
Multi-Video-Source Multiplexing Serial Video Transmitter for MIPI CSI2
The SVT-CS4AP2 supports MIPI CSI2 over MIPI D-PHY. It allows mutilplexing of up to 10 video sources into a CSI2 output stream...
294
15.0
Extended MIPI CSI2 Serial Video Receiver, 64 bits, 8 data lanes, 4 pixels/clock
Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps. This development requires high bandwidth betwe...
295
14.0
40G Ultralink D2D PHY for GF12LP+
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
296
14.0
40G Ultralink D2D PHY for Samsung 7LPP
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
297
14.0
10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
Silicon-proven PHY for PCIe, USB, Ethernet, DisplayPort, and other protocols The Cadence® 10Gbps Multi-Link and Multi-Protocol PHY IP provides a flex...
298
14.0
10Gbps Multi-Protocol PHY IP
Silicon-proven PHY for PCIe, USB, Ethernet, DisplayPort, and other protocols The PHY IP is designed to deliver high eye-margin at low power for backp...
299
14.0
I3C Controller
Controller IP for the MIPI I3C interface The Cadence® IP Family for MIPI® Protocols delivers area-optimized interface IP with the low power and high ...
300
14.0
PCI Express (PCIe) 2.1 Controller
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe® 2.0 is a solution created for less demanding desi...