Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow AMBA AHB / APB/ AXI (186)
arrow CXL (20)
arrow D2D (8)
arrow Gen-Z (6)
arrow HDMI (96)
arrow I2C (97)
arrow Interlaken (2)
arrow MIL-STD-1553 (3)
arrow MIPI (531)
arrow Multi-Protocol PHY (34)
arrow PCI (247)
arrow RapidIO (7)
arrow SAS (6)
arrow SATA (75)
arrow Serdes (108)
arrow Smart Card (7)
arrow UFS (8)
arrow USB (412)
arrow V-by-One (22)
arrow VESA (79)
arrow Other (71)
2025 IP
301
20.0
CXL memory expansion
DenseMem increases effective CXL Type 3 Device memory capacity by a factor of 2x through transparent, in-line memory compression/decompression with mi...
302
17.0
USB 3.x Device IP
SmartDV's USB 3.x Device IP is a silicon-proven, fully featured Universal Serial Bus SuperSpeed device solution purpose-built for SoC designs requirin...
303
16.0
3.3V general purpose I/O for 28nm CMOS
The 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.8V thick oxide MOS devices. It ...
304
16.0
1.8V general purpose I/O for 4nm FinFET
The Sofics 1.8V capable GPIO is an IP macro for on-chip integration. It is a 1.8V general purpose I/O built with a stack of 1.2V MOS FINFET devices. I...
305
16.0
I3C and I2C Combo
It supports standard I3C, high-speed I3C, and Ultra-higher-speed I3C modes. Push-pull operation in I3C modes. Supports I2C standard mode, fast mode, f...
306
16.0
AHB-Lite APB4 Bridge
The Roa Logic AHB-Lite APB4 Bridge is a fully parameterized soft IP interconnect bridge between the AMBA 3 AHB-Lite v1.0 and AMBA APB v2.0 bus protoco...
307
16.0
AHB-Lite General Purpose Memory Module
The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master. All signals defi...
308
16.0
AHB-Lite Multilayer Switch
The Roa Logic AHB-Lite Multi-layer Interconnect is a fully parameterized High Performance, Low Latency Interconnect Fabric soft IP for AHB-Lite. It al...
309
16.0
AHB-Lite Timer
The Roa Logic AHB-Lite Timer IP is a fully parameterized soft IP implementing a user-defined number of timers and functions as specified by the RISC-V...
310
16.0
RISC-V Compliant Platform Level Interrupt Controller
Fully Parameterized & Programmable Platform Level Interrupt Controller (PLIC) for RISC-V based Processor Systems supporting a user-defined number of i...
311
16.0
APB4 General Purpose Input/Output Module
The APB4 GPIO Core is fully parameterised core designed to provide a user-defined number of general purpose, bidirectional IO to a design. The IO a...
312
16.0
APB4 Multiplexer
The AMBA APB v2.0 bus protocol – commonly referred to as APB4 – defines a low-cost interface that is optimized for minimal power consumption and redu...
313
16.0
Open-drain I2C and SMBUS, DDC, CEC & HPD IO offerings
Certus is pleased to offer I2C open-drain IOs across multiple process technologies. The Certus I2C IO can support external supplies of 1.8V, 3.3V and...
314
15.0
3.3V general purpose I/O for 4nm FinFET
The Sofics 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.2V (1.5V overdrive) MOS ...
315
15.0
120dB PDM-to-PCM Digital Microphone Interface
The AR36T05 is a soft macro low-power high-performance digital microphone interface modulator IP. The IP converts stereo/mono 1-bit pulse-density modu...
316
15.0
PCI Express (PCIe) 5.0 Controller
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 5.0 provides the logic required to integrate a r...
317
15.0
PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
SMS5000 is a fully integrated CMOS transceiver that handles the full Physical Layer PCI Express protocol and signaling. It contains all necessary AFE ...
318
15.0
PCIe 3.1 for TSMC
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The 8Gb...
319
15.0
PCIe 5.0 PHY
With sophisticated architecture and advanced technology, KNiulink SerDes PHY IP with PMA and PCS layer is designed for low power and high performance ...
320
15.0
Serial ATA (SATA) I/II PHY IP CORE
SMS6000 is a Serial ATA gen I and gen II compliant PHY IP which supports SAPIS and Serial Attached SCCI (SAS) specifications both at 1.5 Gbp/s and 3.0...
321
15.0
VESA DisplayPort DP 1.4a / eDP 1.4b RX Controller ( LINK ) with HDCP 1.4 / 2.3 , MST
Silicon Library's DisplayPort DP 1.4a / eDP 1.4b RX Controller ( LINK ) works with PHY IPs by Silicon Library or customers' PHYs. HDCP 1.4 / 2.3 and o...
322
15.0
VESA DisplayPort DP 1.4a / eDP 1.4b TX Controller ( LINK ) with HDCP 1.4 / 2.3
Silicon Library’s DisplayPort DP1.4a / eDP 1.4b TX Controller works with PHY IPs by Silicon Library or customers' PHYs. HDCP 1.4 / 2.3 and other vari...
323
15.0
PHY for PCIe 6.0 and CXL for Samsung Automotive
Most advanced PHY and Controller for HPC, AI, ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®)...
324
15.0
USB 3.x Host IP
SmartDV's USB 3.x Host IP is a silicon-proven, fully featured Universal Serial Bus SuperSpeed host controller solution purpose-built for SoC designs r...
325
15.0
USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps
KA13UGUSB20ST001 is USB2.0 physical layer transceiver (PHY) integrated circuits. The PHY can be configured for either an 8-bit or a 16-bit parallel in...
326
15.0
TSMC 13.1Gbps Multi-Protocol Low-Power SerDes IP
It is a 4-lane Serializer/Deserializer IP supporting data rates from 500Mbps to 13.1Gbps. It features flexible architecture for multiple high-speed se...
327
15.0
TSMC 25Gbps SerDes IP with Equalizer
This is a high-performance, multi-protocol serial transceiver IP that supports data rates from 1Gbps to 26Gbps. Built on TSMC 12nm technology, it is d...
328
15.0
SWI3S Manager core IP
Arasan’s SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer the...
329
14.0
10Gbps Multi-Protocol PHY IP
Silicon-proven PHY for PCIe, USB, Ethernet, DisplayPort, and other protocols The PHY IP is designed to deliver high eye-margin at low power for backp...
330
12.0
105dB PCM-to-PDM Stereo Converter
The AR37T01 is a digitally coded stereo PCM-to-PDM conversion IP with 8-bit pattern-code programming. The IP translates parallel PCM input data in...
331
12.0
JESD204b Deser PHY GF 22FDX/ GF 22FDX-PLUS
InCirT offers Deserializer PHY that is implemented in Global Foundries 22FDX CMOS technology. The IP macro offers 2x lanes with data rates from 6.375 ...
332
12.0
JESD204b Ser PHY GF 22FDX/ GF 22FDX-PLUS
InCirT offers Serializer PHY that is implemented in Global Foundries 22FDX CMOS technology. The IP macro offers 1x lane with data rates from 6.375 Gbp...
333
11.0
I2S/Left-Justified/TDM Digital Audio Interface
The AR38U12 is a soft macro IP supporting industry-standard I2S, Left-Justified and Time-Division-Multiplexed (TDM) serial interface to parallel PCM (...
334
11.0
UCIe 2.x Controller IP
SmartDV's UCIe 2.x Controller IP is a silicon-proven, fully featured Universal Chiplet Interconnect Express solution purpose-built for SoC and multi-d...
335
11.0
MIPI C-PHY DSI TX (Transmitter/Host) IP in TSMC 22ULL
The MXL-CPHY-2p5G-DSI-TX-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificati...
336
11.0
MIPI C-PHY/D-PHY Combo 2-Lane CSI-2 TX+ IP in TSMC 40ULP
The MXL-CDPHY-2L-CSI-2-TX+-40ULP is a high-frequency, low-power, low-cost, sourcesynchronous, physical Layer supporting the MIPI Alliance Specificatio...
337
11.0
MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps
The MXL-CD-PHY-CSITX+-ST-28FDSOI is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificati...
338
11.0
MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 22ULP
The MXL-CDPHY-DSI-RX-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification f...
339
11.0
MIPI C-PHY/D-PHY Combo Universal IP, 4.5Gsps/4.5Gbps in TSMC 22ULP
The MXL-CD-PHY-UNIV-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification fo...
340
11.0
MIPI D-PHY
...
341
11.0
MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+
The MXL-DPHY-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification...
342
11.0
MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 22ULL
The MXL-DPHY-CSI-2-TX+-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification...
343
11.0
MIPI D-PHY DSI RX (Receiver/Peripheral) in UMC 22ULP/22ULL
The MXL-DPHY-DSI-RX-U-22ULP-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificat...
344
11.0
MIPI D-PHY IP 4.5Gbps in TSMC N7
The MXL-DPHY-DSI-TX-T-N07 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for ...
345
11.0
MIPI D-PHY Universal IP in TSMC 28HPC+
The MXL-DPHY-UNIV-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificatio...
346
11.0
MIPI D-PHY Universal IP in UMC 28HPC+
The MXL-DPHY-UNIV-U-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for...
347
11.0
MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G
The MXL-MIPI-M-PHY is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used ...
348
11.0
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List
The Digital Blocks DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memo...
349
11.0
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memo...
350
11.0
USB PD IP
SmartDV's USB PD IP is a silicon-proven, fully featured USB Power Delivery solution purpose-built for SoC designs requiring complete PD MAC and protoc...