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1940 IP
301
11.0
MIPI D-PHY
...
302
11.0
MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+
The MXL-DPHY-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification...
303
11.0
MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 22ULL
The MXL-DPHY-CSI-2-TX+-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification...
304
11.0
MIPI D-PHY DSI RX (Receiver/Peripheral) in UMC 22ULP/22ULL
The MXL-DPHY-DSI-RX-U-22ULP-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificat...
305
11.0
MIPI D-PHY IP 4.5Gbps in TSMC N7
The MXL-DPHY-DSI-TX-T-N07 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for ...
306
11.0
MIPI D-PHY Universal IP in TSMC 28HPC+
The MXL-DPHY-UNIV-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificatio...
307
11.0
MIPI D-PHY Universal IP in UMC 28HPC+
The MXL-DPHY-UNIV-U-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for...
308
11.0
MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G
The MXL-MIPI-M-PHY is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used ...
309
11.0
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List
The Digital Blocks DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memo...
310
11.0
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memo...
311
10.0
1-10G Low Power SERDES - TSMC 40G
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
312
10.0
1-15G SERDES PCIe3/HMC SERDES PHY - TSMC 16FF+GL
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
313
10.0
D-phy 1.2 on tsmc 22nm with ultra low power
Arasan Chip Systems announces the immediate availability its MIPI D-PHY IP supporting speeds of upto 2.5 gbps for TSMC 22nm SoC designs. The MIPI D-...
314
10.0
I2C & SMBus Controller
The I2C-SMBUS core implements a serial interface controller for the Inter-Integrated Circuit (I2C) bus and the System Management Bus (SMBus). The cor...
315
10.0
I2C and SPI Master/Slave Controller
The I2CSPI-CTRL is a compact and versatile serial interface controller supporting both SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Cir...
316
10.0
I2C Bus Master Controller Core
The I2C-MS core is a controller for the Inter-Integrated Circuit (I2C) bus. The highly configurable core can implement an I2C bus master, slave, or a ...
317
10.0
12G Ethernet PHY in Samsung (14nm)
The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...
318
10.0
12G Ethernet PHY in TSMC (28nm, 16nm, 12nm)
The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...
319
10.0
12G Ethernet PHY in UMC (28nm)
The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...
320
10.0
32G PHY in GF (12nm, N7)
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and ...
321
10.0
32G PHY in Samsung (10nm, 8nm, 4nm, 5nm, SF2)
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and ...
322
10.0
I3C Device Controller v1.2
The Arasan I3C Device Controller IP Implements Device Controller functionality as defined by the MIPI Alliance’s I3C Specification. The I3C bus is us...
323
10.0
I3C Slave Controller
The Arasan I3C Slave Controller IP Core Implements Slave functionality as defined by the MIPI Alliance’s I3C Specification. The I3C bus is used for va...
324
10.0
25G Ethernet PHY in GF (14nm)
The multi-lane Synopsys Multi-Protocol 25G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and ...
325
10.0
25G Ethernet PHY in TSMC (16nm, 12nm, N7)
The multi-lane Synopsys Multi-Protocol 25G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and ...
326
10.0
25G PHY in GF (14nm, 12nm)
The multi-lane Synopsys Multi-Protocol 25G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and ...
327
10.0
25G PHY in TSMC (16nm, 12nm, N7, N6)
The multi-lane Synopsys Multi-Protocol 25G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and ...
328
10.0
16G PHY in Samsung (14nm, 11nm)
The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...
329
10.0
16G PHY in TSMC (28nm, 16nm, 12nm, N7, N6)
The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...
330
10.0
28G LR Ethernet PHY in GF (12nm)
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and ...
331
10.0
28G LR Ethernet PHY in Samsung (8nm, SF5A)
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and ...
332
10.0
28G LR Ethernet PHY in TSMC (16nm, N7, N6)
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and ...
333
10.0
Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane
The CL12822M4R2JM2LIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP. The CL12822M4...
334
10.0
MAXVY MIPI D-PHY Receiver IP
The MAXVY MIPI D-PHY Receiver IP is a robust high-speed PHY solution designed for receiving MIPI data streams in advanced imaging, display, automoti...
335
10.0
MAXVY MIPI D-PHY Transmitter IP
The MAXVY MIPI D-PHY Transmitter IP is a high-performance PHY solution designed for transmitting high speed data in modern display, camera, automotiv...
336
10.0
PCI Express - Configurable PCI Express 4.0 IP
The Renesas PCIe 4.0 Dual Mode Link Controller IP is compliant with the "PCI Express (PCIe) 4.0 Base Specification". This IP supports the major functi...
337
10.0
PCI Express GEN 3/4 Port SERDES PHY - Samsung 14LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
338
10.0
PCI Express GEN 3/4 Port SERDES PHY - Samsung 7LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...
339
10.0
PCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY ...
340
10.0
PCI Express GEN-3/Display Port SERDES PHY - Samsung 28 28LPP
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
341
10.0
PCI Express GEN-3/SATA3 SERDES PHY - Samsung 28 28FDSOI
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
342
10.0
PCIe 4.0 PHY
With sophisticated architecture and advanced technology, KNiulink SerDes PHY IP with PMA and PCS layer is designed for low power and high performance ...
343
10.0
PCIe 4/5 Refenece Clock PLL with SSCS - GLOBALFOUNDRIES 12LP+
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
344
10.0
PCIe 5.0 PHY NCS in TSMC (N7, N6, N6C, N5, N3P)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...
345
10.0
PCIe/HCSL Differential IO Buffer - TSMC 16FFC
Analog Bits offers a unique set of IP's that is used for various SERDES applications. This unique IP is used for sending source clocks to SERDES for P...
346
10.0
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
347
10.0
PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP+
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
348
10.0
PCIe3 SSCG PLL - TSMC 12FFC
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
349
10.0
PCIe3 SSCG PLL - TSMC 16FFC
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 ...
350
10.0
PCIe4 Ethernet SERDES PHY - TSMC N5
Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY...
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