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1891 IP
301
20.0
TSMC 4nm (N4P) 1.2V/1.8V/2.5V Failsafe GPIO Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
302
20.0
TSMC 4nm (N4P) 1.8V SD/eMMC IO
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...
303
20.0
TSMC 4nm (N4P) 1.8V SD/eMMC PHY
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...
304
20.0
TSMC 4nm (N4P) 2.5V Basekit Libraries
Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic librarie...
305
20.0
TSMC 4nm (N4P) 2.5V Basekit Libraries, multiple metalstacks
Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic librarie...
306
20.0
TSMC 5nm (N5) 1.2V/1.8V Basekit Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
307
20.0
TSMC 5nm (N5) 1.2V/1.8V Failsafe GPIO Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
308
20.0
TSMC 5nm (N5) 1.2V/1.8V Failsafe GPIO Libraries, multiple metalstacks
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
309
20.0
TSMC 5nm (N5) 1.2V/1.8V I3C Libraries
Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...
310
20.0
TSMC 5nm (N5) 1.2V/1.8V/2.5V Failsafe GPIO Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
311
20.0
TSMC 5nm (N5) 1.2V/1.8V/2.5V GPIO Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
312
20.0
TSMC 5nm (N5) 1.2V/1.8V/2.5V GPIO Libraries, multiple metalstacks
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
313
20.0
TSMC 5nm (N5) 1.8V SD/eMMC IO
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...
314
20.0
TSMC 5nm (N5) 1.8V SD/eMMC PHY
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...
315
20.0
TSMC 5nm (N5) 2.5V Basekit Libraries
Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...
316
20.0
TSMC 5nm (N5)1.8V SD/eMMC PHY, multiple metalstacks
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...
317
20.0
TSMC 6nm (6FF) 3.3V GPIO
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
318
20.0
TSMC 6nm (6FF) 3.3V SMBUS (I2C) IO
Synopsys Inter-Integrated Circuit (I2C) I/O library is used for two wire interfaces to connect low-speed devices like EEPROM, A/D, and D/A converters ...
319
20.0
TSMC 6nm (N6) 3.3V Basekit Libraries
Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic librarie...
320
20.0
TSMC 7nm (7FF) 1.8V LVDS
Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...
321
20.0
TSMC 7nm (7FF) 3.3V GPIO
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
322
20.0
TSMC 7nm (7FF) 3.3V SMBUS (I2C) IO
Synopsys Inter-Integrated Circuit (I2C) I/O library is used for two wire interfaces to connect low-speed devices like EEPROM, A/D, and D/A converters ...
323
20.0
Synopsys PCIe 4.0 PHY IP for TSMC N7
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
324
18.0
1.8V general purpose I/O for 4nm FinFET
The Sofics 1.8V capable GPIO is an IP macro for on-chip integration. It is a 1.8V general purpose I/O built with a stack of 1.2V MOS FINFET devices. I...
325
18.0
Die-2-die interfaces for chiplets
Analog I/OS and power line ESD solutions All voltage domains (0.75V to 5V) Additional voltage (e.g. 12V in 28nm proven)...
326
18.0
on-chip ESD protection
Analog I/OS and power line ESD solutions All voltage domains (0.75V to 5V) Additional voltage (e.g. 12V in 28nm proven)...
327
18.0
Analog I/O - low capacitance, low leakage
Analog I/OS and power line ESD solutions All voltage domains (0.75V to 5V) Additional voltage (e.g. 12V in 28nm proven) Ultra-low leakage Low para...
328
17.0
56Gbps LR SerDes IP on TSMC 16/12nm
Credo is a world leading SerDes Technology Company offers silicon proven SerDes IP from 1G to 112G data rates. Features include the lowest power i...
329
17.0
56Gbps LR SerDes IP on TSMC 7nm
Credo is the world leading SerDes Technology. SerDes PMA is silicon proven IP offers in TSMC 7nm processes. Features include excellent insertion loss...
330
17.0
28Gbps LR SerDes IP on TSMC 28nm
Credo is the world leading SerDes Technology Company offers silicon proven SerDes IP from 1G to 112G data rate. Features include excellent insertio...
331
17.0
28Gbps MR SerDes IP on TSMC 28nm
Credo is the world leading SerDes Technology Company offers silicon proven SerDes IP from 1G to 112G data rates. This SerDes PMA is silicon proven...
332
17.0
AXI2APB Bridge
Truechip's AXI2APB IP provides chip designers and architects, an efficient way to connect AXI & APB based IPs with reduced latency, power, and area....
333
16.0
3.3V general purpose I/O for 28nm CMOS
The 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.8V thick oxide MOS devices. It ...
334
16.0
AHB-Lite APB4 Bridge
The Roa Logic AHB-Lite APB4 Bridge is a fully parameterized soft IP interconnect bridge between the AMBA 3 AHB-Lite v1.0 and AMBA APB v2.0 bus protoco...
335
16.0
AHB-Lite General Purpose Memory Module
The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master. All signals defi...
336
16.0
AHB-Lite Multilayer Switch
The Roa Logic AHB-Lite Multi-layer Interconnect is a fully parameterized High Performance, Low Latency Interconnect Fabric soft IP for AHB-Lite. It al...
337
16.0
AHB-Lite Timer
The Roa Logic AHB-Lite Timer IP is a fully parameterized soft IP implementing a user-defined number of timers and functions as specified by the RISC-V...
338
16.0
RISC-V Compliant Platform Level Interrupt Controller
Fully Parameterized & Programmable Platform Level Interrupt Controller (PLIC) for RISC-V based Processor Systems supporting a user-defined number of i...
339
16.0
APB4 General Purpose Input/Output Module
The APB4 GPIO Core is fully parameterised core designed to provide a user-defined number of general purpose, bidirectional IO to a design. The IO a...
340
16.0
APB4 Multiplexer
The AMBA APB v2.0 bus protocol – commonly referred to as APB4 – defines a low-cost interface that is optimized for minimal power consumption and redu...
341
16.0
USB2.0 Host Transceiver PHY
USB 2.0 HOST Transceiver is a fully integrated PHY Core which is a super-set of HOST PHY with High Speed (HS), Full-Speed (FS) and Low-Speed Transceiv...
342
15.0
2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter
The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture of t...
343
15.0
120dB PDM-to-PCM Digital Microphone Interface
The AR36T05 is a soft macro low-power high-performance digital microphone interface modulator IP. The IP converts stereo/mono 1-bit pulse-density modu...
344
15.0
Camera SLVS-EC 3.0 Transmitter 10.0Gbps 8-Lane
* The CL12811M8TIP10000 TXPHY supports 8 TX DATA lanes for up to 10Gbps application. A wide range phase-locked clock is embedded in the IP to suppor...
345
15.0
PCIe 5.0 PHY
With sophisticated architecture and advanced technology, KNiulink SerDes PHY IP with PMA and PCS layer is designed for low power and high performance ...
346
15.0
High Performance Second Generation Extended MIPI CSI2 Receiver
Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps. This development requires high bandwidth betwee...
347
15.0
MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations. It complies with MIPI® CSI2 V2.0 and DPHY1.2 spec...
348
15.0
MIPI D-PHY CSI-2 RX (Receiver) in TSMC 16FFC
he MXL-DPHY-CSI-2-RX-T-16FFC is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification f...
349
15.0
MIPI D-PHY CSI-2 RX+ (Receiver) IP in UMC 40ULP
The MXL-DPHY-CSI-2-RX+ is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PH...
350
15.0
MIPI D-PHY Universal IP in TSMC 40LP for Automotive
The MXL-DPHY-UNIVERSAL-T-40LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard fo...