Design & Reuse
1480 IP
551
4.0
12-bit 250MHz Decimation filter with 43 taps
The ODT-DSP-DEC-43T250M-T16 is a 12-bit 250MHz Decimation filter with 43 taps in a 12/16nm CMOS process. The 43 Tap Decimation filter reduces the o...
552
4.0
12-bit 250MHz interpolation filter with 43 taps
The ODT-DSP-INT-43T250M-T16 is a 12-bit 250MHz interpolation filter with 43 taps in a 12/16nm CMOS process. The 43 Tap interpolation filter increas...
553
4.0
12-bit, 250MSPS ADC on TSMC 7nm
The ODT-ADS-12B250M-7T is an ultra-low power ADC designed in a 7nm CMOS process. This 12-bit, 250MSPS ADC supports input signals up to 100MHz and f...
554
4.0
12-bit, 8 GSPS High Performance Swift™ DAC in 16nm CMOS
The ODT-DAC-12B8G-16 is a high performance current steering 12-bit 8GSPS DAC on 16nm CMOS process that operates at an update rate of up to 8GSPS. The ...
555
4.0
12bit, 1.6 GSPS ADC Ultra Low Power
The ODT-ADS-12B1P6G-7T-222 is an ultra high-performance time-interleaved ADC designed in a 16nm CMOS process. This 12-bit, 1.6GSPS ADC supports input...
556
4.0
14-bit, 300 MSPS Ultra Low Power ADC in 28nm CMOS
The ODT-ADP-14B300M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni Design's groundbreaki...
557
4.0
14-bit, 50 MSPS Ultra Low Power ADC in 28nm CMOS
The ODT-ADP-14B50M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni Design's groundbreakin...
558
4.0
High-speed clock receiver circuit operating up to 2.5 GHz with low output jitter.
The ODT-CRX-2P5G-16 is a high-speed clock receiver circuit capable of operating up to 2.5 GHz with low output jitter. The CRX uses a high-speed signa...
559
4.0
Ultra-Low-Power (<140nA) Bandgap Voltage Reference in 40nm CMOS
The ODT-REF-40LP-SV1P8-ULP140N is an ultra-low power CMOS bandgap reference designed in a 40nm standard CMOS process without needing the use of any bi...
560
4.0
Ultra-Low-Power Bandgap Voltage Reference in GF 22 FDX
The ODT-REF-GF22FDX-SV1P8 is a high-performance reference current and voltage generator. The block incorporates a proprietary architecture to achieve ...
561
4.0
Ultra-Low-Power Bandgap Voltage Reference in TSMC 4nm CMOS
The ODT-REF-SV1P2-4T is a high-performance reference current and voltage generator. The block incorporates a proprietary architecture to achieve high ...
562
4.0
TVM - Temperature and Voltage Monitor
The ODT-TVM-ULP-001C-16FFCT is an ultra-low power temperature and voltage monitor designed in a 16nm standard TSMC process. This IP operates over the ...
563
4.0
TVM - Temperature and Voltage Monitor with interrupt
The ODT-TVM-INT-001C-12 is an ultra-low power temperature and voltage monitor designed in a 12nm standard process. This IP operates over the entire t...
564
4.0
TVM - Temperature and Voltage Monitor with interrupt
The ODT-TVM-INT-001C-16 is an ultra-low power temperature and voltage monitor designed in a 16nm standard process. This IP operates over the entire t...
565
4.0
TVM - Temperature/Voltage Monitor in 28nm CMOS
The ODT-TVM-ULP-001C-28 is an ultra-low power temperature and voltage monitor designed in a standard 28nm CMOS process. The IP operates over the entir...
566
4.0
8x 14-bit, 2.4GSPS Swift™ DAC with 8x interpolation filters
The ODT-AFE-8D8IF-16 is an ultra-high performance AFE designed in a 16nm process. The AFE includes 8 DACs along with 8 interpolation filters. This AFE...
567
2.5
SATA 3 Host Controller on ARRIA V FPGA
The LDS SATA 3 HOST AR5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Stratix IV GX FPGA. T...
568
2.5
SATA 3 Host Controller on ZYNQ
The LDS SATA 3 HOST XZ7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA. The LDS SATA 3 HOST...
569
2.5
SATA 3 HOST IP on ARRIA 10 FPGA
The LDS-SATA3-HOST-A10GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a INTEL ARRIA 10 GX FPGA. The L...
570
2.5
SATA Device Controller on Kintex 7
The LDS SATA 3 DEVICE XK7 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 FPGA. The LDS SATA...
571
2.5
SATA HOST 3 ON KINTEX 7 Ultrascale
The LDS SATA 3 HOST XK7U IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 Ultrascale speed grade 2 FPGA. The...
572
2.5
SATA HOST 3 ON VIRTEX 7 GTH
...
573
2.5
SATA Host 6G Controller on Kintex 7
The LDS SATA 3 HOST XK7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 speed grade 2 FPGA. The LDS SATA 3 ...
574
2.5
SATA Host on Xilinx Zynq Artix 7
The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS SATA 3 H...
575
2.5
LDS SATA RECORDER IP ON ARTIX 7
...
576
2.5
LDS SATA RECORDER ON ZYNQ
...
577
2.5
Xilinx Kintex 7 NVME HOST IP
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD....
578
2.5
Xilinx Ultra Scale NVME Host IP
The LDS NVME HOST K7U IP is one of the most flexible NVME HOST IP in the market. It has been done for beginners and expert in NVMe to drive NVMe PC...
579
2.5
Xilinx Ultra Scale Plus SATA HOST IP
The LDS_SATA3_HOST_GTHE4 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Ultra Scale Plus GTHE4 FPGA. The LDS_SATA3_...
580
2.5
Xilinx ZYNQ NVME HOST IP
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD....
581
2.5
Virtex 7 GTX SATA 3 Host Controller
The LDS SATA 3 HOST XV7X IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 7 GTX speed grade 2 FPGA. The LDS SA...
582
2.5
NVMe Host Recorder on Mini-ITX Zynq 7
The LDS NVME HOST RECORDER IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD. The register file interface simplify the manag...
583
2.5
NVME-HOST-IP VIRTEX 7
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD....
584
2.5
ZYNQ SATA 3 AHCI Host Controller with Linux Driver
The LDS SATA 3 HOST AHCI XZ7 IP incorporates the AHCI registers model, the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed gr...
585
2.0
SATA 3 Host Controller on Xilinx Artix 7
The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS_SATA3_HO...
586
2.0
LDS SATA RECORDER ON KINTEX 7
...
587
2.0
High performance 1.8V reference current and voltage generator
The ODT-REF-16FFCT-SV1P8 is a high-performance reference current and voltage generator. The block incorporates a proprietary architecture to achieve h...
588
2.0
ARINC 429 Synchronous Transmitter Receiver
The M429T1R1 macro implements a synchronous single-chip ARINC 429 Transmit and Receive Controller Macro capable of linking one CPU to one ARINC 429 bu...
589
2.0
TVM - Temperature/Voltage Monitor in 28nm CMOS
The ODT-TVM-ULP-001C-28 is an ultra-low power temperature and voltage monitor designed in a standard 28nm CMOS process. The IP operates over the entir...
590
2.0
TVM - Temperature/Voltage Monitor in 40nm CMOS
The ODT-TVM-ULP-001C-40 is an ultra-low power temperature and voltage monitor designed in a standard 40nm CMOS process. The IP operates over the entir...
591
1.0
I2C Master
The MI2CM macro implements a synchronous single-chip I2C Master only Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is ca...
592
1.0
I2C MAster Slave
The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus...
593
1.0
I2C Slave
The MI2CS macro implements a synchronous single-chip I2C Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried ...
594
1.0
14-bit, 600 MSPS Ultra Low Power ADC in 28nm CMOS
The ODT-ADP-14B600M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni Design's groundbreaki...
595
1.0
SATA 2 HOST ON CYCLONE 5 GX
The LDS SATA 2 HOST_C5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a ALTERA Cyclone V GX FPGA. The...
596
1.0
SATA Device Controller on Altera Arria II GX
The LDS SATA DEVICE AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The...
597
1.0
SATA Device on Stratix IV GX
The LDS SATA DEVICE STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA STRATIX IV GX FPGA. ...
598
1.0
SATA Device on Virtex 6
The LDS SATA DEVICE XV6 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA D...
599
1.0
SATA Host Controller
The LDS SATA HOST STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Startix IV GX FPGA. Th...
600
1.0
SATA HOST Controller on Cyclone IV GX
The LDS SATA HOST C4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Cyclone IV GX FPGA. The ...